Methods and apparatuses for providing stacked-die devices

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S686000, C257S777000, C257S787000, C257SE25006, C257SE25013, C257SE25018, C257SE25021, C257SE25027, C257SE23085

Reexamination Certificate

active

10917142

ABSTRACT:
Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and associated wires are protected by an encapsulant leaving an upper portion of each interconnection exposed. For one embodiment of the invention the encapsulant is a stencil-printable encapsulant and the upper portion of the interconnection is exposed by use of a patterned stencil during application of the encapsulant.

REFERENCES:
patent: 5040052 (1991-08-01), McDavid
patent: 5422435 (1995-06-01), Takiar et al.
patent: 6414384 (2002-07-01), Lo et al.
patent: 6448506 (2002-09-01), Glenn et al.
patent: 6489676 (2002-12-01), Taniguchi et al.
patent: 6813157 (2004-11-01), Chang
patent: 2002/0121687 (2002-09-01), Winderl
patent: 2002/0135057 (2002-09-01), Kurita
patent: 2002/0196650 (2002-12-01), Chang
patent: 2003/0042564 (2003-03-01), Taniguchi et al.
patent: 2005/0121764 (2005-06-01), Mallik et al.
patent: 200-178414 (2000-06-01), None
patent: 2001-223227 (2001-08-01), None
PCT Search Report mailed Dec. 6, 2005 for PCT/US2005/027103.

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