Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-01-04
2011-01-04
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S021000, C714S037000, C714S039000, C714S049000, C714S051000, C714S724000, C714S728000, C714S733000, C714S734000, C714S738000, C714S739000, C717S135000, C703S003000, C703S004000, C703S014000, C703S015000, C703S019000, C703S020000, C703S021000
Reexamination Certificate
active
07865795
ABSTRACT:
Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.
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patent: 4500993 (1985-02-01), Jacobson
patent: 6011830 (2000-01-01), Sasin et al.
patent: 7613599 (2009-11-01), Bade et al.
patent: 7680645 (2010-03-01), Li et al.
patent: 2004/0044508 (2004-03-01), Hoffman, Jr.
Nirmaier Thomas
Spirkl Wolfgang
Dicke Billig & Czaja, PLLC
Qimonda AG
Trimmings John P
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