Methods and apparatus to support error-checking of variable...

Details Methods and apparatus to support error-checking of variable... Methods and apparatus to support error-checking of variable...

2006-11-21

2006-11-21

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000

Reexamination Certificate

active

07139963

ABSTRACT:
A given data packet is parsed into words and a final partial word that are processed (depending on size) in each of multiple successive stages of logic circuitry. Similarly sized words are processed at one stage of the logic circuit. Smaller and smaller modulo-2 components of the final partial word are processed at successive stages of logic circuitry. Based on this technique of processing modulo-2 components in different stages, the corresponding multi-stage logic circuit can be implemented in a low cost logic circuit such as an FPGA device instead of a custom-masked ASIC.

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