Methods and apparatus for system testing of processors and compu

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

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G01R 3128

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active

059789468

ABSTRACT:
In one aspect of the present invention, an apparatus is provided for testing a processor running a software program. The apparatus includes a bus having control, data and address lines and a device assigned at least one address. The bus connects the device to the processor. The apparatus includes a multiple input signature register having a plurality of parallel input terminals connected to the data lines. The apparatus includes a control unit having first and second input terminals connected to the address and control lines respectively. The control unit is adapted to enabling the parallel input terminals of the multiple input signature register in response to detecting on the address and control lines at least one preselected triggering event executed by the software program to a preselected address of the device. The apparatus includes a signature comparator adapted to comparing a test signature number from the multiple input signature register to a reference signature number.

REFERENCES:
patent: 4520440 (1985-05-01), Buonomo et al.
patent: 4864570 (1989-09-01), Savaglio et al.
patent: 5301199 (1994-04-01), Ikenaga et al.
patent: 5583786 (1996-12-01), Needham
patent: 5608867 (1997-03-01), Ishihara
Designer's Guide to Testable ASIC Devices,Wayne Maurice Needham, (Van Nostrand Reinhold, New York, 1991), pp. vii-x and 10-15, 34-37, 63-178.

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