Methods and apparatus for reducing memory errors

Details Methods and apparatus for reducing memory errors Methods and apparatus for reducing memory errors

2007-10-30

2007-10-30

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S718000

Reexamination Certificate

active

11116625

ABSTRACT:
In a first aspect, a first method is provided for reducing memory errors. The first method includes the steps of (1) detecting at least one error in data output from a first physical memory unit (PMU) of a memory; (2) detecting at least one error in data output from a second PMU of the memory; and (3) setting a bit indicating respective data output from a plurality of PMUs includes errors. Numerous other aspects are provided.

REFERENCES:
patent: 5519830 (1996-05-01), Opoczynski
patent: 6141737 (2000-10-01), Krantz et al.
patent: 7173852 (2007-02-01), Gorobets et al.
patent: 7224607 (2007-05-01), Gonzalez et al.

Affiliated with

Also associated with

Rating

Methods and apparatus for reducing memory errors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatus for reducing memory errors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for reducing memory errors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3840642