Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-07-05
2004-01-20
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C702S117000, C716S030000
Reexamination Certificate
active
06681353
ABSTRACT:
BACKGROUND OF THE INVENTION
A typical field programmable gate array (FPGA) device is a customizable integrated circuit (IC) device having, at least initially, a matrix of non-dedicated gates. A user customizes the FPGA device to perform one or more specific functions. In particular, the user forms customized FPGA circuitry within the device by specifying configuration details such as interconnections between gates, initial operating states, etc. Some FPGA devices include random access memory (RAM), e.g., 16 kilobytes, which the customized FPGA circuitry can utilize during operation.
A designer of a circuit board typically performs a test-and-debug process on a circuit board prior to permitting the circuit board to be manufactured on a large scale for commercial use. If the circuit board includes an FPGA device (i.e., if the circuit board has an FPGA device mounted thereon), the circuit board designer may wish to examine the signals entering and/or leaving the device. To examine these signals, the circuit board designer typically connects a logic analyzer, storage oscilloscope, etc. (hereinafter generally referred to as a logic analyzer) to the FPGA device. The designer then uses the logic analyzer to capture samples of these signals, and compares the captured samples to an expected set of samples. This process enables the designer to identify and correct any design problems (e.g., programming errors) relating to the FPGA device.
One approach to connecting the logic analyzer to the FPGA device involves designing the circuit board such that it includes a circuit board connector mounted thereon, and circuit board connections (metallic etching) leading from the mounted circuit board connector to various leads or pads of the FPGA device. With this approach (hereinafter referred to as the “built-in approach”), the designer can then simply attach a cable from the logic analyzer to the connector mounted on the circuit board in order to electronically access the FPGA device.
Another approach to connecting the logic analyzer to an FPGA device involves attaching wires to portions of the circuit board. In this approach (hereinafter referred to as the “soldering approach”), the circuit board designer typically enlists the assistance of a person skilled in soldering wires to circuit boards. The designer instructs that person to solder, or hardwire, colored wires to particular metallic circuit board vias which lead to the FPGA device. The designer then attaches a cable from the logic analyzer to the soldered colored wires in order to electronically access the FPGA device.
SUMMARY OF THE INVENTION
Unfortunately, there are certain deficiencies in conventional approaches for electronically accessing an FPGA device using a logic analyzer. For example, the built-in approach, which requires the circuit board designer to include a mounted circuit board connector and circuit board connections leading from the connector to pads of the FPGA device, requires sacrificing a substantial amount of circuit board area for the connector (the connector “footprint”), and the circuit board connections. Often the placement of such connections has routing and signal integrity consequences on neighboring areas of the circuit board as well.
Additionally, the soldering approach, which requires a person to solder colored wires to circuit board vias leading to the FPGA device, is prone to mistakes. That is, the person soldering the colored wires to the vias can easily make mistakes by soldering a wrong-colored wire to a particular via, soldering a properly-colored wire to the wrong via, etc. Moreover, the addition of the solder and wires to the circuit board can change the electrical characteristics of the circuit board connections increasing the likelihood of distorting the signal samples captured from the circuit board. Such distortions can disrupt critical timing paths, particularly when dealing with high speed signals, thus making the samples unreliable. Also, the time and cost involved in having a skilled person meticulously solder wires to the circuit board can be substantial.
Furthermore, both the built-in and soldering approaches require the use of a logic analyzer to capture signals entering and/or leaving the FPGA device. A typical logic analyzer is expensive (e.g., $100K) and requires periodic maintenance. Additionally, a circuit board designer wishing to test and debug an FPGA device on a circuit board using the logic analyzer must invest time and effort into setting up and connecting the logic analyzer prior to the test-and-debug process.
Additionally, improvements in circuit board technologies have made the above-identified conventional approaches relatively expensive and difficult endeavors from non-monetary perspectives. In particular, surface mounting techniques, IC packages with inaccessible pads (e.g., Ball Grid Arrays), the trend towards using smaller pitches, and the trend towards placing modules on both sides of circuit boards have exacerbated the difficulties in connecting a logic analyzer to a circuit board in order to electronically access FPGA devices.
In contrast, the invention is directed to techniques which use a test circuit within an FPGA device to obtain a trace of a digital signal used by normal operating circuitry of the FPGA device. The test circuit stores the trace in memory of the FPGA device which is accessible without the need of a logic analyzer (e.g., accessible in a memory mapped or I/O mapped manner). Accordingly, the test circuit can operate as an embedded logic analyzer within the FPGA device. As such, the deficiencies of the conventional built-in approach (e.g., sacrificing circuit board area) and the soldering approach (e.g., time and effort soldering wires to the circuit board, signal integrity drawbacks, etc.) for obtaining electronic access to mounted FPGA devices using external logic analyzers are avoided.
One arrangement of the invention is directed to a computer system having a bus, a processor coupled to the bus, and an FPGA device coupled to the bus. The FPGA device includes (i) normal operating circuitry for performing a normal operating function of the FPGA device, and (ii) a test circuit coupled to the normal operating circuitry. The test circuit is configured to obtain a trace of a digital signal used by the normal operating circuitry. In particular, the test circuit receives, from the processor and through the bus, a control signal enabling capture of the digital signal. The test circuit then captures samples of the digital signal in response to the control signal, and stores the captured samples of the digital signal in the test circuit. The captured samples form the trace of the digital signal. Accordingly, the circuit board designer can avoid the deficiencies of using a logic analyzer by performing a test-and-debug procedure using the test circuit of the FPGA device.
In one arrangement, the test circuit of the FPGA device includes a controller and memory. The controller has a counter, and counter initialization circuitry coupled to the counter. The counter initialization circuitry is configured to (i) receive an initialization signal from the processor and through the bus, and (ii) initialize contents of the counter in response to the initialization signal. The contents of the counter identify memory locations of the memory for storing samples of the digital signal. Accordingly, the controller has an effective mechanism for addressing the memory of the test circuit.
In one arrangement, the controller further includes counter modification circuitry coupled to the counter. The counter modification circuitry modifies the contents of the counter in response to the control signal. In this arrangement, the control signal directs capture of the digital signal within the memory locations of the memory.
In one arrangement, the controller of the test circuit includes a selector that (i) receives a select signal from the processor and through the bus, and (ii) selects a portion of the normal operating circuitry from which to capture the samples of the digital signal
Chapin & Huang , L.L.C.
EMC Corporation
Huang, Esq. David E.
Moise Emmanuel L.
LandOfFree
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