Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2006-02-28
2006-02-28
Dildine, R. Stephen (Department: 2133)
Electronic digital logic circuitry
With test facilitating feature
C326S093000
Reexamination Certificate
active
07005885
ABSTRACT:
A synchronous circuit implements a bypass mode for use in conjunction with an inductive-capacitive (“LC”) buffer. The LC buffer receives differential conventional clock signals, and generates buffered differential conventional clock signals. A synchronous circuit, such as a latch, includes at least two clock receivers. The conventional clock signal is input to the first clock receiver, such as a transistor, and an auxiliary clock is input to a second clock receiver. The conventional clock signal provides timing for the synchronous circuit under a normal mode of operation, and the auxiliary clock signal provides timing for the synchronous circuit under a test mode of operation at a frequency lower than the conventional clock signal.
REFERENCES:
patent: 6741094 (2004-05-01), Ogawa
patent: 6765414 (2004-07-01), Keshavarzi et al.
Mehta, S.K.; Seth, S.C.; Einspahr, K.L.; Synthesis for testability by two-clock control; VLSI Design, 1997. Proceedings., Tenth International Conference on; Jan. 4-7, 1997; pp. 279-283.
Aeluros, Inc.
Dildine R. Stephen
Stattler Johansen & Adeli LLP
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