Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-17
2003-09-30
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S778000, C438S931000
Reexamination Certificate
active
06627535
ABSTRACT:
This invention relates to methods and apparatus for forming films on a substrate and in particular, but not exclusively, to forming low k etch stop films and devices containing such films. For the purposes of this specification the term low k refers to dielectric constants of 3.5 or less.
Damascene and dual damascene processing is becoming more prevalent in the manufacture of semiconductor wafers and in particular where copper is used as the interconnect metal. This is because the plasma etching of copper is relatively difficult and it is therefore preferred to etch formations in the dielectric layer and then deposit copper into the etched structure to fill it. Any excess copper can then be removed from the surface for example by chemical mechanical polishing leaving an inlay of copper in the etched features.
In dual damascene processing two separate but connected features are etched in respective dielectric layers one line above the other. Thus a trench may be cut in the upper layer and vias may be formed in the lower layer to connect the trench to contact points in an underlying layer. Examples of such structures are discussed in an article entitled Dual Damascene Challenges, Dielectric Etch by Peter Singer in the August 1999 edition of Semiconductor International.
A common approach to creating dual damascene features is to deposit an etch stop layer between the two layers of dielectric so that the etch stop layer gives a good “end point” signal to the automated etching equipment as breaks through the first layer. Such closed loop control is preferred because it enables more precise control of the etched features than an open loop timed etch.
The etch stop layer therefore tends to need to have a relatively high selectivity for the etch process relative to the upper layer so that it is etched significantly more slowly giving time for control to take place.
Commonly, these days, it is desirable that the whole dielectric structure has a low k value and this leads one to the desire to have an etch stop layer which also has a low k value.
Additionally a silane-based plasma-formed silicon nitride has been used as an etch stop layer in association with a silicon dioxide type layer, however such silicon nitride would usually have a k value of about 7.5 compared to a standard silicon dioxide k value of 4.1 and the perceived low k requirement that k is less than 3.5. Silicon carbide has been proposed as an alternative etch stop material but its k value is 9 to 10 and this still results in significant increases in the k value of the dielectric stack. Silicon nitride layers have also been found to be problematic in that they create a good water barrier and many low k processes rely on water being able to be forced out of the dielectric layer during processing.
Further, current silicon nitride technology is not necessarily compatible with the chemistry used to form the low k layers.
A discussion of these problems is contained in WO-A-99/41423, but the conclusion of that patent application is that a good etch stop layer for this situation should have a significant oxide content. A large number of proposed solutions are set out but they appear to require stacks of layers having significantly different k values.
From one aspect the invention consists in a semiconductor device including a dual damascene structure formed in a dielectric stack, the stack comprising an upper layer having first formation etched therein, an intermediate etch stop layer and a lower layer having a second formation etch therein, the second formation being contiguous with the first, each of the layers having a dielectric constant k≦3.5 and more preferably below 3.0 and the etch stop layer having a selectivity of at least 2.5:1 relative to the upper layer.
Preferably the etch stop layer is integral with the lower layer and it is particularly preferred that the etch stop layer is formed of nitrogen doped silicon carbide.
In a particularly preferred arrangement the k value of the etch stop layer is substantially equal to that of the other layers in the stack. Surprisingly, it has been found that the k value of the nitrogen doped silicon carbide can be adjusted depending on the amount of nitrogen doping which takes place. It is therefore, at least to an extent, possible to match the k value of the etch stop layer, with that of the other dielectric layers.
As has already been indicated above, that the etch stop layer may be integral with the lower layer, because the k value of the nitrogen doped silicon carbide is sufficiently low to be a low k dielectric material in its own right.
Thus from a second aspect the invention consists in a low k dielectric layer formed of nitrogen doped silicon carbide.
From a further aspect the invention consists in a method of forming a low k film on a substrate comprising:
(a) positioning the substrate on a support in a chamber; and
(b) supplying to the chamber, in gaseous or vapour form, a silicon-containing organic compound and nitrogen in the presence of a plasma to deposit a nitrogen doped silicon carbide film on the substrate.
The silicon containing organic compound may be an alkylsilane and more specifically it may be tetraalkylsilane. It is particularly preferred that the silicon containing organic compound is tetramethylsilane.
The film may be deposited on a substrate positioned at or below room temperature and RF power may be supplied during the deposition of the film.
Although the invention has been defined above it is to be understood it includes any inventive combination of the features set out above or in the following description.
REFERENCES:
patent: 4647472 (1987-03-01), Hiraki et al.
patent: 5225032 (1993-07-01), Golecki
patent: 5244698 (1993-09-01), Ishihara et al.
patent: 5514604 (1996-05-01), Brown
patent: 5635423 (1997-06-01), Huang et al.
patent: 1 059 664 (2000-12-01), None
patent: WO 99/56310 (1999-04-01), None
patent: WO 99/33102 (1999-07-01), None
patent: WO 99/41423 (1999-08-01), None
patent: 99/41423 (1999-08-01), None
patent: WO 00/19498 (2000-04-01), None
Beekman Knut
MacNeil John
Wilby Robert John
Ghyka Alexander
Trikon Holdings Ltd.
Volentine & Francos, PLLC
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