Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-10-08
2001-03-13
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S736000, C324S073100, C324S537000, C324S763010
Reexamination Certificate
active
06202185
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to testing circuitry, and more particularly to methods and apparatus for facilitating the scan testing of such circuitry.
Scan testing is a well-known technique for testing circuitry to determine whether or not the circuitry has been properly designed to function as required under all operating conditions, and also to determine whether the circuit itself has been fabricated properly and without defects. In some designs, scan registers are added in addition to the actual logic registers to implement the scan chain. For those designs, the actual logic registers are not used in the scan chain and are thus not affected.
In other cases, the logic registers, themselves, are used for scanning out data. In this case, the logic registers serve as logic registers in normal operation. However, during scan testing, these same registers are used to shift their stored values along the scan chain. This latter case reduces hardware in the circuit because dedicated scan registers do not need to be added.
As a consequence of using the same registers for both normal operation and scan testing, the output of these registers toggles with scan data during the scanout procedure. If these same outputs drive bistable circuits (e.g., J-K flip-flops), the toggling of the register output could change the state of the bistable. Therefore, even if the scan register data is scanned back into the device, the original state of the machine is lost. It is because of the loss of state that this type of scanout is destructive. Therefore, using the prior art technique, it is not possible to stop a circuit, scan out its register contents, and then continue on where the circuit was stopped. Instead, the circuit has to be re-initialized and its input pattern rerun.
In view of the foregoing, it is an object of this invention to provide improved methods and apparatus for scan testing circuits.
It is another object of this invention to make it possible for normal operation of a circuit to be stopped, to have the data scanned out, and then to have the original state recovered so that the circuit can continue running from the point just before scan testing began.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished by providing circuitry having register circuits, each having an input gate configured to selectively pass a data signal applied to that register, and a master stage configured to store a data signal passed by the input gate of that register. Each register circuit has an interstage gate configured to selectively pass a data signal stored by the master stage of that register, and a slave stage configured to store a data signal passed by the interstage gate of that register. Inter-register gates are operatively arranged to selectively pass a data signal stored by the master stage of an associated respective first one of the registers to the master stage of an associated respective second one of the registers for storage by the master stage of that second one of the registers. The master stages of all of the registers and the inter-register gates are connected in a series of alternating master stages and inter-register gates.
Normal mode circuitry is configured to alternately enable the input gates and the interstage gates of each register. This enables the contents of each master stage to be stored by the associated slave stage. Normal mode circuitry also disables the inter-register gates, which are not used during normal operation. Scan mode circuitry is configured to disable the input gates and the interstage gates to preserve the outputs of all register slave stages of the circuit during scanout. Alternate ones of the inter-register gates are enabled by the scan mode circuitry.
In a preferred embodiment, a feedback gate is configured to selectively pass a data signal stored by the slave stage of each of the registers to the master stage of that register for storage by that master stage. The scan mode circuitry is further configured to enable the feedback gates while disabling the input gates, the interstage gates, and the inter-register gates. In a preferred embodiment, restoration mode circuitry is configured to selectively enable one of the input gates and the feedback gates and to disable the interstage gates and the inter-register gates. The selection between the input gates and the feedback gates may be based on the phase of a clock signal.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
REFERENCES:
patent: 4856002 (1989-08-01), Sakashita et al.
patent: 4864579 (1989-09-01), Kishida et al.
patent: 5008618 (1991-04-01), Van Der Star
patent: 5047710 (1991-09-01), Mahoney
patent: 5166604 (1992-11-01), Ahanin et al.
Altera Corporation
Egbert, III Walter M.
Fish & Neave
Jackson Robert R.
Moise Emmanuel L.
LandOfFree
Methods and apparatus for facilitating scan testing of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for facilitating scan testing of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for facilitating scan testing of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2517354