Methods and apparatus for constructing low-density parity...

Details Methods and apparatus for constructing low-density parity... Methods and apparatus for constructing low-density parity...

2005-03-16

2008-11-04

Chaudry, M. Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07447972

ABSTRACT:
Methods and apparatus for constructing a parity check matrix for use in a low-density parity check (LDPC) coding scheme are provided. The apparatus includes at least one index generator for generating row indexes of “1”s, which indicate row positions of the “1”s in each column of the parity check matrix, wherein the index generator is implemented by a modular shift register generator that generates a row index of a “1” at each clock.

REFERENCES:
patent: 5954838 (1999-09-01), Leshem et al.
patent: 6505319 (2003-01-01), Kodama
patent: 6567465 (2003-05-01), Goldstein et al.
patent: 6715121 (2004-03-01), Laurent
patent: 6757122 (2004-06-01), Kuznetsov et al.
patent: 2002/0042899 (2002-04-01), Tzannes et al.
patent: 2003/0037298 (2003-02-01), Eleftheriou et al.
patent: 2003/0079172 (2003-04-01), Yamagishi et al.
patent: 2004/0034828 (2004-02-01), Hocevar
patent: 2004/0186992 (2004-09-01), Matsumoto
patent: 2007/0011568 (2007-01-01), Hocevar
patent: 2-195457 (1990-08-01), None
patent: 5-135482 (1993-06-01), None
patent: 2000-331439 (2000-11-01), None
patent: 2003-115768 (2003-04-01), None
patent: 2003-198383 (2003-07-01), None
patent: 2004-33554 (2004-04-01), None
patent: 2004-36460 (2004-04-01), None
patent: 200406666 (2004-05-01), None
patent: 200412722 (2004-07-01), None
patent: WO 02/09976 (2002-12-01), None
patent: WO 02/099976 (2002-12-01), None
U.S. Patent Publication No. 2003/0037298 corresponds to Japanese Patent Publication No. 2003-115768.
U.S. Patent Publication No. 2004/0186992 A1 corresponds to Japanese Patent Publication No. 2003-198383.
U.S. Patent No. 6,505,319 corresponds to Japanese Patent Publication No. 2000-331439.
Search Report issued Mar. 8, 2006 by European Patent Office re: European Application No. 05 25 3997 (4 pp).
MacKay, David J.C.. “Good Error-Correcting Codes Based on Very Sparse Matrices,”IEEE Transactions on Information Theory,vol. 45, No. 2, Mar. 1999 (pp. 399-431).
Sorokine Vladislav et al. “Gallager Codes for CDMA Applications—Part I: Generalizations, Constructions and Performance Bounds,”IEEE Transactions on Communications,vol. 48, No. 10, Oct. 2000 (pp. 1660-1668).
Vasic, Bane. “Structured Iteratively Decodable Codes Based on Steiner Systems and Their Application in Magnetic Recording,” IEEE Global Telecommunications Conference, San Antonio, TX: vol. 5, Nov. 25, 2001 (pp. 2954-2960).
Xilinix Logicore. “Linear Feedback Shift Register v3.0,” Product Specification, Mar. 28, 2003 (pp. 1-19). <http://www.xilinix.com/ipcenter/catalog/logicore/docs/lfsr.pdf>.
Vasic, B., “Structured Iteratively Decodable Codes Based on Steiner Systems and Their Application in Magnetic Recording”, IEEE Global Telecommunications Conference, 2001, Globecom '01, vol. 5, 25-29, Nov. 2001, pp. 2954-2960.
Office Action issued in corresponding Taiwanese Patent Application No. 94117622 dated May 7, 2008.
US 2002/0042899 and WO 02/099976, cited in the Taiwanese Office Action, were previously cited in the Information Disclosure Statement filed Nov. 27, 2006.

Affiliated with

Also associated with

Rating

Methods and apparatus for constructing low-density parity... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatus for constructing low-density parity..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for constructing low-density parity... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4031369