Methods and apparatus for clock domain conversion in digital...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses

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C713S500000, C713S600000

Reexamination Certificate

active

06954869

ABSTRACT:
Methods and apparatus are provided for clock domain conversion in digital processing systems. The methods include operating a first circuit in a fast clock domain with a fast clock and operating a second circuit in a slow clock domain with a slow clock. To transfer signals from the fast clock domain to the slow clock domain, a first synchronization signal is asserted during each fast clock cycle in which a slow clock edge occurs. A fast signal is transferred from the fast clock domain to the slow clock domain on a fast clock edge when the first synchronization signal is asserted. To transfer signals from the slow clock domain to the fast clock domain, a second synchronization signal is asserted during each fast clock cycle that immediately follows a slow clock edge. A slow signal is transferred from the slow clock domain to the fast clock domain on a fast clock edge when the second synchronization signal is asserted.

REFERENCES:
patent: 5535377 (1996-07-01), Parks
patent: 5548620 (1996-08-01), Rogers
patent: 6516362 (2003-02-01), Magro et al.
patent: 6549593 (2003-04-01), Rumreich et al.

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