Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
1999-07-21
2001-10-30
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S149000
Reexamination Certificate
active
06310813
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to Dynamic Random Access Memory (DRAM) devices and controlling methods therefor, and more particularly to apparatus and methods for controlling the refreshing of DRAM devices.
BACKGROUND OF THE INVENTION
DRAM devices are widely used in consumer and commercial applications. As is well known to those having skill in the art, a DRAM device generally includes an array of memory cells, each of which includes one or more capacitors or other energy storage devices. Since charge generally leaks from the capacitors, it is well known that DRAM devices must be refreshed periodically, so as not to lose the data that is stored therein. Accordingly, DRAM devices generally are designed to be refreshed at a DRAM refreshing rate that is related to a DRAM refreshing time.
Unfortunately, DRAM refreshing operations may be time consuming, which can thereby reduce the overall speed of DRAM devices and of apparatus (systems) that employ the DRAM device. Moreover, DRAM refreshing generally consumes power which may reduce the operational time of battery-powered systems that employ DRAM devices.
DRAM devices often are used as part of a graphics card or other graphics system that may be used to display graphical data on a monitor. For example, graphics cards are widely used with personal computers to allow efficient display of static or animated graphical data on the monitor of the personal computer. As is well known to those having skill in the art, when DRAM devices are used as part of graphic display systems, the DRAM may be divided into a frame buffer that stores pixel data, a z buffer that is used to display three-dimensional data, and a texture storing zone that stores texture or other pattern data. As is also known to those having skill in the art, in a graphical display system, the monitor generally is refreshed periodically at a display refreshing rate, in order to allow smooth changes of animation data on the display and/or to account for the persistence characteristics of the display.
Due to the widespread use of DRAM devices, for example in connection with graphic display systems, it is desirable to provide improved DRAM devices and systems employing DRAM devices, that can reduce the impact of DRAM refreshing on overall speed and/or power consumption.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved DRAM devices such as are used in graphic memory apparatus, and methods of controlling the same.
It is another object of the present invention to provide methods and apparatus for controlling refreshing operations of DRAM devices that can reduce the power that is consumed by refreshing operations.
It is still another object of the present invention to provide DRAM devices and apparatus and methods for controlling DRAM devices that can reduce the time that is expended for refreshing operations.
These and other objects can be provided, according to the present invention, by bypassing the refreshing of a portion of a DRAM device when carrying out a refreshing operation on the DRAM device. By bypassing the refreshing of a portion of the DRAM device when carrying out a refreshing operation, the operational speed of the DRAM device and of systems that use the DRAM device can be increased, and/or the power consumption thereof can be decreased.
More specifically, graphic memory apparatus according to the present invention, include a DRAM device that is divided into a frame buffer zone that supplies pixel data for a display and at least one other zone, such as a z buffer and/or a texture storing zone. According to the present invention, refreshing of the frame buffer zone is bypassed when carrying out a refreshing operation on the DRAM device. Stated differently, at least one other zone is refreshed at a DRAM refreshing rate that is independent of a display refreshing rate. In contrast, the frame buffer zone is refreshed at the display refreshing rate that is independent of the DRAM refreshing rate. It has been recognized, according to the present invention, that the display refreshing operation takes place on the frame buffer at a display refreshing interval, so that it is not necessary to also refresh the frame buffer portion of the DRAM as part of the DRAM refreshing operation.
Accordingly, in contrast with conventional DRAM systems that may carry out a DRAM refresh operation on the entire DRAM, the present invention need only refresh those portions of the DRAM device that will not be refreshed as a result of the display refreshing operation. Stated differently, it has been recognized that the time that is expended for a screen refreshing operation generally is shorter than that for the DRAM refreshing operation. Accordingly, the DRAM cells that are the subject of the screen refreshing operation need not require a DRAM refreshing operation.
In a preferred embodiment of the present invention, indications of a starting DRAM address and an ending DRAM address for the frame buffer may be stored. A refreshing operation is performed only on those DRAM addresses that fall outside the starting address and the ending address. More specifically, a counter may be provided that counts in response to a clock signal, to produce a counter output signal. A comparator system compares the counter output signal to the starting address and to the ending address, to provide the counter output signal to an address decoder for the DRAM device when the output of the counter is outside the starting address and the ending address, and to withhold the counter output signal from the address decoder when the counter output is between the starting address and the ending address.
More preferably, the comparator system includes a first switching apparatus that transmits the stored indication of the ending address in response to a first signal, and a second switching apparatus that transmits the counter output signal in response to an inverted second signal. A first latching apparatus is responsive to the first and second switching apparatus to latch the indication of the ending address or the counter output signal. The address decoder is responsive to the first latching apparatus. A comparator is provided that compares the counter output signal and the indication of the starting address, to generate the second signal. Finally, an ANDing apparatus ANDs the clock signal and the second signal, to generate the first signal. High speed and/or reduced power refreshing operations for DRAM devices thereby may be provided.
REFERENCES:
patent: 5751930 (1998-05-01), Katsura et al.
patent: 5818464 (1998-10-01), Wade
patent: 6167484 (2000-12-01), Boyer et al.
Hoang Huan
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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