Electronic digital logic circuitry – Reliability – Fail-safe
Reexamination Certificate
2000-10-02
2001-11-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Reliability
Fail-safe
C326S083000, C326S086000, C326S009000
Reexamination Certificate
active
06320406
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to differential data line receivers and more particularly to methods and apparatus for preventing such circuits from switching on noise in the absence of an input signal.
2. Description of Background Art
Low voltage differential signals (LVDS) are being used more and more to meet the need for faster data transmission. Because these differential signals can typically have a valid input voltage swing, between positive and negative signal levels, of as low as 350 mV, they tend to be much faster and use less power than conventional rail-to-rail circuits. Typically, such circuits can operate at speeds up to 655 MHz, while dissipating only one-eighth the power of conventional rail-to-rail circuits. Standards such as ANSI TIA/EIA-644 and IEEE 1596.3 dictate the use of these low voltage differential signals in system applications. In addition, these low voltage differential circuits are inherently more immune to common-mode noise and common-mode signal reflections.
FIG. 1
a
shows a LVDS receiver
10
with positive and negative inputs of the differential signal V
IA
and V
IB
, respectively, and output V
0
.
FIG. 1
b
show the waveforms for a typical receiver circuit, where the differential input signal V
IA
11
and V
IB
12
have a swing of 400 mVolts (1.4-1.0 V). Internally, the circuit generates signal V
ID
13
, which switches between +0.4 and −0.4 volts and supplies a single-ended output signal V
0
14
, which switches at the application's TTL or CMOS digital HIGH V
OH
and LOW V
OL
levels with rise and fall times, t
r
and t
f
, respectively.
A problem with typical LVDS circuits has been that the receiver can switch, and even oscillate, on noise signals in the absence of an input signal. This is particularly true when the data line is terminated in low impedance. This operating state can occur when the data source is turned OFF, for example in the case of wired-OR signaling being used in data bus arbitration, or when the interconnecting cable is removed or damaged, causing a short.
To overcome the problems discussed above, fail-safe circuits are commonly used to prevent LVDS receivers from switching on input noise. Current LVDS fail-safe solutions require either external components with subsequent reduction in signal quality or integrated solutions with limited application. An external fail-safe circuit used to provide a known receiver output in the absence of an input signal is shown in FIG.
2
. This circuit consists of a differential line driver
20
, an LVDS receiver
26
, a differential cable for the positive
21
and negative
22
signals, a cable terminating resistor
24
, a positive signal pull-up resistor
23
tied to V
dd
, and a negative signal pull-down resistor
25
tied to circuit GND or V
ss
. This approach maintains a DC offset voltage in the absence of a valid input signal, but the presence of the bias network can unbalance the driver output loop, causing additional leakage currents in the resistors, which can possibly distort and reduce the amplitude of the receiver's output signal. This increases the likelihood of the circuit switching or oscillating on input noise in the absence of a valid input signal. In addition, this solution tends to lower the input signal magnitude, reducing the differential noise margin and also can introduce an offset in the receiver, thereby requiring larger input signals to make it switch.
FIG. 3
shows one typical method of solving this problem using an integrated solution, including a resistor network, which applies a steady-state bias voltage to the undriven input pins. The circuit consists of a differential line driver
30
, a differential cable for the positive
31
and negative
32
signals, two external pull-up resistors
33
-
34
, an LVDS receiver
35
, and fail-safe logic implemented as a NAND gate
36
. The NAND gate
36
for the fail-safe function is shown attached effectively in parallel with the input of the receiver
35
. In operation, in the absence of an input signal this approach pulls both inputs to the positive bias voltage level. The fail-safe logic senses this condition with both inputs of the NAND gate
36
going HIGH, driving the output LOW. This signal in turn can be used to drive the output of the receiver
35
to a known logic state. However, the pull-up to V
CC
tends to be defeated by the applied voltage and as a result, these circuits are often limited to open-circuit conditions or are restricted to only certain, limited operating conditions.
A second integrated fail-safe circuit, which relies on bias currents integrated internally into the receiver, is illustrated in FIG.
4
. This configuration consists of a differential line driver
40
, a differential cable for the positive signal
41
and the negative signal
42
, a terminating resistor
43
, and an integrated LVDS receiver
44
with bias sources consisting of a positive current source
45
and negative current sink
46
. These bias sources provide a current through the termination resistor
43
to assure that a DC voltage is maintained across the resistor when a valid input signal is not present, thereby maintaining the receiver output at a known voltage level. Although these small bias currents do not appreciably affect the input signal magnitude, one disadvantage of this existing fail-safe solution is that the bias currents are not always able to generate the required differential when an external common-mode voltage is applied. Increasing these bias currents to alleviate this problem results in additional bus loading during normal operation. Also, the offset created when pulling the two differential signals apart increases the input signal magnitude required by the receiver to switch, and can cause pulse skew, which is the difference between the time needed for the receiver to switch from LOW-to-HIGH and the time required to switch form HIGH-to-LOW.
What is needed is a fail-safe method and apparatus for providing a known LVDS receiver output in the absence of an input signal that does not affect the performance of the receiver during normal operation, and without the need for external components. The invention disclosed herein addresses this need.
SUMMARY OF THE INVENTION
In its broader aspects, the present invention is a fail-safe circuit that provides a known logic level output in the absence of a differential input signal. Included are a relatively high-speed receiver having inputs coupled to a first and second differential input, and having an output. Also included is a window comparator that is also coupled to the first and second differential inputs. The window comparator includes first and second comparators, each having a first and a second differential input. The first input of the first comparator is coupled to the second input of the second comparator and to the second input of the receiver, while the second input of the first comparator is coupled to the first input of the second comparator and to the first input of the receiver. A timer is also provided, coupled to the output of the receiver. A logic circuit is provided, having inputs coupled to the outputs of the first and second comparators and to the output of the timer. The logic circuit provides an active output only when all inputs are active. Finally, an output buffer is provided, having inputs coupled to the output of the receiver and to the output of the logic circuit. The output buffer provides an output corresponding to the output of the receiver when the output of the logic circuit is inactive, and provides an output having a predetermined logic state when the logic circuit is active.
According to other aspects of the invention there is an active fail-safe method and apparatus for an LVDS receiver that uses a window comparator circuit to monitor the differential voltage at the receiver's input pins and drive the output to a known logic HIGH state in the absence of an input signal, for example, when the input differential signal is less than a predetermined threshold
Carvajal Fernando D.
Gingerich Kevin J.
Morgan Mark W.
Brady III W. James
Moore J. Dennis
Tan Vibol
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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