Methodology to reduce SOI floating-body effect

Details Methodology to reduce SOI floating-body effect Methodology to reduce SOI floating-body effect

2007-04-05

2008-08-12

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S151000, C438S303000, C438S305000, C438S514000, C438S595000, C438S518000, C257SE21345, C257SE21633, C257SE21634

Reexamination Certificate

active

07410876

ABSTRACT:
A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode (207) disposed on a substrate (203); (b) creating first (213) and second (214) pre-amorphization implant regions in the substrate such that the first and second pre-amorphization implant regions are asymmetrically disposed with respect to said gate electrode; (c) creating first (219) and second (220) spacer structures adjacent to first and second sides of the gate electrode, wherein the first and second spacer structures overlap the first and second pre-amorphization implant regions; and (d) creating source (217) and drain (218) regions in the substrate adjacent, respectively, to the first and second spacer structures.

REFERENCES:
patent: 5780912 (1998-07-01), Burr et al.
patent: 6534373 (2003-03-01), Yu
patent: 6855592 (2005-02-01), Lee
patent: 6916716 (2005-07-01), Goad et al.
patent: 7118980 (2006-10-01), Jain
patent: 7354839 (2008-04-01), Wei et al.
patent: 2005/0136623 (2005-06-01), Tan et al.
patent: 2005/0164461 (2005-07-01), Chen et al.
patent: 2006/0043430 (2006-03-01), Feudel et al.
patent: 2006/0216899 (2006-09-01), Chen
patent: 2006/0252213 (2006-11-01), Chen
patent: 2006/0284249 (2006-12-01), Chen et al.
patent: 2007/0037326 (2007-02-01), Chen et al.
patent: 2007/0252205 (2007-11-01), Hoentschel et al.
Wei, H.F. et al., “Improvement of Breakdown Voltage and Off-State Leakage in Ge-Implanted SOI n-MOSFETs”; IEEE, 1993, pp. IEDM 93-739-742.
Ohno, T. et al., “Supp. of the Parasitic Bipolar Effect in Ultra-Thin-Film nMOSFETs/SIMOX by Ar Ion Implant. into Source/Drain Regions”; 1995, IEEE, pp. IEDM 95-627-630.
Chen, Vincent M.C. and Woo, Jason C.S., “Tunneling Source-Body Contact for Partially-Depleted SOI MOSFET”; IEEE Trans. on Elect. Dev., V. 44, No. 7, Jul. 1997, pp. 1143-1147.
Chang, D. et al., “Efficacy of Ar in Reducing the Kink Effect on Floating-Body NFD/SOI CMOS”; Proceedings 1998 EIII International SOI Conference; Oct. 1998; pp. 155-156.
Matloubian, M., “Smart Body Contact for SOI MOSFETs”, Semiconductor Process and Design Center, Texas Instruments Inc.; Intl. SOI Conf., 1989, pp. 128-129.
Bergaud, C. et al., “Formation of Implanted Piezoresistors Under 100-NM Thick for Nanoelectromechanical Systems”; IEEE, 2002, pp. 360-363.
Borland, John O. et al., “Applying Equivalent Scaling to USJ Implantation”; Semiconductor International; Jan. 1, 2005; 8 pages; www.reed-electronics.com/semiconductor.
Borland, John.; “Implantation and Annealing Options for 65 nm Node SDE Formation”; Apr. 1, 2003; 2 pages; www.reed-electronics.com/semiconductor.

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