Methodology of locating faults of scan chains in logic...

Details Methodology of locating faults of scan chains in logic... Methodology of locating faults of scan chains in logic...

2006-07-11

2006-07-11

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C714S025000

Reexamination Certificate

active

07076707

ABSTRACT:
For a plurality of logic integrated circuits, initial value vectors associated with flip-flops are retrieved from each of corresponding scan chain sets. The initial value vectors of the same corresponding scan chain set are compared with each other so as to identify elements with fixed values in the initial value vectors. When the total number of the elements with fixed values reaches a predetermined percentage, the elements having fixed values are selected as a golden pattern of the corresponding scan chain set. During the testing, an initial value vector of a scan chain of a logic integrated circuit to be tested is compared with the golden pattern associated with the scan chain, so as to determine whether a faulty flip-flop exists in the scan chain of the logic integrated circuit to be tested.

REFERENCES:
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patent: 5570376 (1996-10-01), Kunda et al.
patent: 5831992 (1998-11-01), Wu
patent: 6490702 (2002-12-01), Song et al.
patent: 6553329 (2003-04-01), Balachandran
patent: 6865706 (2005-03-01), Rohrbaugh et al.

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