Methodology for selectively testing portions of an...

Details Methodology for selectively testing portions of an... Methodology for selectively testing portions of an...

2006-06-13

2006-06-13

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07062693

ABSTRACT:
A method and apparatus are disclosed for easily reconfiguring a scan chain test of a subset of scan blocks within a digital integrated circuit chip. To mitigate timing violations in the scan test of scan chains, alternative embodiments to implement a transfer of scan data to a next scan block are implemented.

REFERENCES:
patent: 2002/0194565 (2002-12-01), Arabi
patent: 2003/0140293 (2003-07-01), Motika et al.

Affiliated with

Also associated with

Rating

Methodology for selectively testing portions of an... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methodology for selectively testing portions of an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methodology for selectively testing portions of an... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3677898