Methodology for achieving dual gate oxide thicknesses

Details Methodology for achieving dual gate oxide thicknesses Methodology for achieving dual gate oxide thicknesses

2000-05-01

2001-05-15

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S264000, C438S981000

Reexamination Certificate

active

06232244

ABSTRACT:

TECHNICAL FIELD
The present invention relates to manufacturing semiconductor devices having a plurality of operating voltages and, more particularly, to manufacturing ultra large scale integration and high density semiconductor devices with submicron design features and a plurality of gate oxide thicknesses.
BACKGROUND ART
Escalating demands for high density and performance associated with ultra large scale integration require semiconductor devices with design features of 0.25 microns and under, e.g. 0.18 microns, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor technology for forming gate oxides.
Conventional semiconductor devices comprise a substrate having various electrically isolated regions, called active regions, in which individual circuit components are formed. The active region typically includes source/drain regions of a transistor formed in the semiconductor substrate or epitaxial layer, spaced apart by a channel region. A gate electrode for switching the transistor is formed on the channel with a gate oxide layer therebetween. The quality and thickness of the gate oxide are crucial for the performance and reliability of the finished device.
The speed of circuit components is affected by the time required to charge and discharge parasitic load capacitances in the circuit. Since a lower operating voltage results in a shorter time to charge and discharge the load capacitances, faster circuitry is typically attained by reducing the operating voltage. In order to reduce the operating voltage, however, the threshold voltage (V
&tgr;
) of the transistor must also be lower. One way to lower the threshold voltage is to reduce the thickness of the gate oxide, which contributes proportionally to the body effect (&ggr;) and, hence, the threshold voltage.
The reliability of circuit components is also affected by the thickness of the gate oxide. For example, if an excessive potential is applied to the gate electrode, the gate dielectric breaks down and causes a short circuit to occur between the gate electrode and typically the source of the transistor. The potential at which the gate dielectric breakdown occurs is termed the “breakdown voltage” and is related to the thicknesses of the gate oxide. Since the gate oxide must be thick enough to prevent gate dielectric breakdown, a higher operating voltage necessitates a thicker gate oxide to support a higher breakdown voltage.
Certain semiconductor devices have circuit components operating at different voltages. For example, a FLASH memory device comprises core circuitry that stores the memory bits and peripheral circuitry for decoding row and column addresses. As another example, speed-critical components of a microprocessor are typically operated at a lower voltage, but less speed-critical components of the microprocessor are operated at a higher voltage. For enhanced operating speed, it is desirable to operate the core circuitry at a fairly low voltage, such as about 1.8V to about 2V. In this situation, it is desirable to use relatively thinner gate oxides for the transistors. The peripheral circuitry, which is not speed-critical, however, is typically operated at a higher voltage, such as 5V, for enhanced reliability due to relatively thicker gate oxides. For example, a gate oxide having a thickness of about 40 Å can be effective for circuitry running at about 1.8V to about 2V. However, circuitry operating at about 5V can use a gate oxide region about 55 Å, about a third thicker and less susceptible to gate dielectric breakdown.
A typical, conventional approach to manufacturing gate oxides to different thicknesses is illustrated in
FIGS. 1A through 1F
. In
FIG. 1A
a semiconductor substrate
100
is prepared according to known techniques comprising doped, monocrystalline silicon or an epitaxial layer formed thereon. The thermal oxide layer
102
is formed on the substrate
100
typically as a by-product of creating field oxide isolation structure
104
, as by etching and filling a shallow trench as depicted in
FIG. 1A
or by local oxidation of silicon (LOCOS). The field oxide isolation structure
104
separates and electrically isolates active region
106
from active region
108
. In this example, active region
106
is for the peripheral circuitry of a FLASH memory and, hence, will have a thicker gate oxide; core active region
108
, on the other hand, will have a thinner gate oxide.
Referring to
FIG. 1B
, a photoresist mask
110
is deposited on thermal oxide layer
102
and patterned, as by photolithography, to create an opening
112
under which the active region
108
requiring the thinner gate oxide is to be formed. The opening
112
comprises vertically aligned side walls
114
in the photoresist mask
110
and a bottom surface exposing a portion
116
of the thermal oxide layer
102
.
Referring to
FIG. 1C
, the area
120
of the core active region
108
immediately below the main surface of the substrate
100
is nitridated by ion implantation of nitrogen through opening
112
of the mask
110
and through the exposed thermal oxide portion
116
. The mask
110
protects the peripheral active region
106
from the nitrogen implantation. The result of the nitrogen implantation step, illustrated in
FIG. 1D
, is a nitridated area
120
in the core active region
108
below the exposed thermal oxide portion
116
. Ion implantation damages the crystal lattice of the substrate
100
and, hence, lowers the quality of gate oxides grown thereon. Although the wafer may be annealed to repair the implantation damage, the attendant loss of implanted nitrogen into the thermal oxide portion
116
is considerable, greatly reducing the effectiveness of the nitrogen implantation.
Referring to
FIG. 1E
, the photoresist is stripped and the thermal oxide layer including portion
116
is removed, leaving isolation structure
104
, core active region
108
, and peripheral active region
106
. At this point, illustrated in
FIG. 1F
, gate oxide is grown on the active regions by thermal oxidation. In the core active region
108
, the nitridated area
120
retards the thermal oxidation rate, resulting in a thin gate oxide
130
. On the other hand, in the peripheral active region
106
, the thermal oxidation rate is not retarded by implanted nitrogen, having been protected by mask
110
, resulting in a thicker gate oxide
132
. In sum, the conventional approach to manufacturing semiconductor devices with dual gate oxide thicknesses is to selectively implant nitrogen through the thermal oxide layer
102
, allowing thinner gates oxides to be grown in nitridated active regions.
A disadvantage with the conventional method of nitrogen implantation through a thermal oxide is that the thermal oxide layer typically lacks uniformity in thickness. Consequently, it is difficult to control the ion implantation of nitrogen to achieve the desired concentration of nitrogen atoms near the surface of the substrate. For example; at thinner areas of the thermal oxide, nitrogen atoms may be implanted too deeply, over which the gate oxide may be grown too thick, reducing production throughput and yield.
Conventionally, the thermal oxide layer is not stripped to expose the main surface of the substrate to a more consistent nitrogen implantation. A deposited photoresist mask is difficult to remove from the silicon substrate. Stripping the photoresist mask typically leaves some residue contamination on the substrate which adversely affects the quality of the gate oxide grown thereupon, especially in ultra large scale integrated semiconductor circuits. As mentioned earlier, some amount of the implanted nitrogen is lost into the thermal oxide layer during annealing; however, if the thermal oxide layer is stripped to expose the main surface of the substrate and the wafer is annealed, the attendant nitrogen loss is significantly and disadvantageously increased. In fact, the loss of nitrogen

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