Methodology and apparatus for implementing write combining

Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying

Reexamination Certificate

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C710S030000

Reexamination Certificate

active

10977235

ABSTRACT:
Write-combining in a computer system that uses a push model is set forth herein. In one embodiment, the method comprises creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer assigned to a write-combinable range in response to a flush request to flush the buffer, and sending (pushing) these packets to the network I/O device.

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patent: 2004/0015503 (2004-01-01), Smith et al.
patent: 2005/0071534 (2005-03-01), Kwatra
Thomas R. Craver, “Hyper-Threading Technology and Write Combining Store Buffers: Understanding, Detecting, and Correcting Performance Issues”, Intel Software Network, Jul. 18, 2005, http://www.intel.com/cd/ids/developer/asmo-na/eng/20465.htm?pm=Y., 11 pages.
Raoul A.F. Bhoedjang, et al., “User-Level Network Interface Protocols”, IEEE, Nov. 1998, pp. 53-60.

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