Method using quasi-planar double gated fin field effect...

Details Method using quasi-planar double gated fin field effect... Method using quasi-planar double gated fin field effect...

2005-05-24

2005-05-24

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S593000, C438S149000, C438S154000, C438S157000, C257S348000, C257S349000

Reexamination Certificate

active

06897111

ABSTRACT:
A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are then formed on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is formed from at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is formed from at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor being in contact with the thyristor.

REFERENCES:
patent: 6229161 (2001-05-01), Nemati et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6448586 (2002-09-01), Nemati et al.
patent: 6458632 (2002-10-01), Song et al.
patent: 6492662 (2002-12-01), Hus et al.
Farid Nemati and James D. Plummer, A Novel Thyristor-based SRAM Cell (t-Ram) for High-Speed, Low-Voltage, Giga-scale Memories, Center for Integrated System, Stanford University Stanford, CA 94305, 1999 IEEE.

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