Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-31
2001-02-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S633000, C438S634000, C438S638000, C438S782000
Reexamination Certificate
active
06184128
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to methods of forming trenches, holes and interconnects using a dual damascene process.
BACKGROUND ART
Conventional semiconductor devices typically comprise a semiconductor substrate, normally made of monocrystalline silicon, and a plurality of dielectric and conductive layers formed thereon. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Such interconnection lines, made of metal interconnect materials, generally constitute a limiting factor in terms of size (width) and various functional characteristics of the integrated circuit. As such, there exists a need to provide a reliable interconnection structure having a small size yet capable of achieving higher operating speeds, improved signal-to-noise ratio and improved reliability.
Using a dual damascene process, semiconductor devices are patterned with several thousand openings for conductive lines and vias which are filled with a conductive metal, such as aluminum or copper, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel signal lines of conductive metal in the insulating layers of multilayer substrate on which semiconductor devices are mounted.
Damascene (single damascene) is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings also are formed. In the standard dual damascene process, the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via openings and the pattern is anisotropically etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with a resist material which is exposed to a second mask with the image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and grooves are filled metal.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. Although standard dual damascene offers advantages over other processes for forming interconnections, it has a number of disadvantages and problems. For example, the edges of the via openings in the lower half of the insulating layer are not only poorly defined because there are two etching steps; but also because the via edges are unprotected during the second etching. Thus, improvements are needed in the standard dual damascene process to eliminate the poor edge definition of the via openings.
Another problem associated with edge definition of the via openings is illustrated in FIG.
8
. This problem is frequently encountered when an low k materials are employed in the semiconductor device. In particular,
FIG. 8
shows the poor sidewall profile due to undesirable over-etching of the insulating material when the photoresist is removed or stripped. This is commonly referred to as undercutting. Undercutting is often caused when removing or stripping conventional photoresists from substrates during dual damascene processing. While the undesirable over-etching is shown in connection with the via, the same problem may occur with the trench. The over-etching leads to malformed metal vias and/or trenches as well as the trapping of air between the metal via (and/or trench) and the insulating material. This consequently degrades the electrical properties of the resultant electronic devices.
In processes where transparent layers are employed, especially in instances where transparent layers are employed over reflective layers, it is difficult to adequately pattern (for example, due to poor critical dimension control and/or undercutting). As a result, antireflection (ARC) layers may be employed. But ARCs tend to unnecessarily complicate the processing. T is therefore desirable to improve printability of photoresists while eliminating the use of ARCs.
SUMMARY OF THE INVENTION
The present invention provides dual damascene methods useful with low k insulation materials. The present invention also provides methods of processing semiconductors having low k insulation materials while not deleteriously effecting the low k insulation materials (that is, by not causing undercutting of the low k insulation layers). The present invention provides methods of adequately forming interconnects and using short wavelength light and/or ultra-thin photoresists. The present invention involves forming high quality interconnects and thus provides methods of forming electronic devices having desirable electrical properties. In particular, the sidewalls of trenches and vias formed during a dual damascene process according to the present invention are of high quality in that they do not exhibit undesirable bowing, air trapping or other deformities. The trenches and vias formed during a dual damascene process according to the present invention are of high quality because of the improved printability when using short wavelength light and/or ultra-thin photoresists. Another advantage obtainable with the present invention is that it is not necessary to use ARCs, especially where insulation layers containing silicon nitride are employed.
In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second photoresist have a thickness of about 1,500 Å or less.
In another embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first ultra-thin photoresist having a thickness of about 1,500 Å or less thereby exposing a portion of the first low k material layer; removing the first ultra-thin photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second ultra-thin photoresist having a thickness of about 1,500 Å or less thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions o
Bell Scott A.
Levinson Harry J.
Lyons Christopher F.
Nguyen Khanh B.
Wang Fei
Advanced Micro Devices , Inc.
Amin, Eschweiler & Turocy, LLP
Gurley Lynne
Niebling John F.
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