Method to thin down copper barriers in deep submicron...

Details Method to thin down copper barriers in deep submicron... Method to thin down copper barriers in deep submicron...

2000-07-13

2002-05-21

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S703000, C438S758000

Reexamination Certificate

active

06391783

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices used in integrated circuits, and specifically to a method of forming an in-situ copper barriers in deep sub-micron geometries.
BACKGROUND OF THE INVENTION
Existing, ex-situ barriers will be difficult to implement as the geometries shrink and aspect ratios continue to increase. Insufficient step coverage will lead to poor barrier properties and results in integration problems, especially in the presence of copper (Cu).
U.S. Pat. No. 5,821,168 to Jain describes a process for forming a semiconductor device by nitriding an insulating layer then covering it with a thin adhesion layer to form a diffusion barrier film. An adhesion layer, that may include magnesium, titanium or the like, is formed over the diffusion barrier layer. A composite copper layer is then deposited within a via opening in the adhesion layer coated insulating layer and planarized to form a dual inlaid structure, for example. The process does not require a separate diffusion barrier due to the formation of the diffusion barrier layer from a portion of the insulating layer. The adhesion layer provides a strong adhesion between the composite copper and the nitrided oxide portions.
U.S. Pat. No. 5,747,360 to Nulman describes a method for metallizing semiconductor materials that includes two processing steps. The first step involves depositing an alloy layer on the semiconductor surface in a single step from a single source. The layer may be an alloy of conductive metal, such as aluminum, and an Alloy Material such as hafnium, tantalum, magnesium, germanium, silicon, titanium, titanium nitride, tungsten and/or a composite of tungsten. The second step, a layer of the conductive metal, such as aluminum, is deposited over the alloy layer.
U.S. Pat. No. 5,876,798 to Vassiliev describes a method of forming high quality films of fluorinated silicon oxide suitable for use a intermetal dielectrics by tight control over the deposition conditions by means of CVD (chemical vapor deposition) at reduced pressure using fluorotriethoxysilane (FTES) and tetra-exthyloxysilane (TEOS) as precursors together with ozone (mixed with oxygen). In a second embodiment, TEOS is omitted and only FTES is used.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to eliminate the need for an ex-situ copper barrier layer.
A further object of the present invention is fabricate an in-situ copper barrier layer that inhibits copper diffusion.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, an etched dielectric layer, over a conductive layer, over a semiconductor structure are provided. The etched dielectric layer is preferably comprised of FSG and has a via hole and an exposed periphery. The etched dielectric layer is treated with at least one alkaline earth element source, preferably Ca(HCO
3
)
2
, and RMgBr and RMgCl Grignard reagents to form an in-situ metal barrier layer within the dielectric layer exposed periphery. A metal plug, preferably comprised of copper, is formed within the via hole wherein the in-situ metal barrier layer prevents diffusion of the metal from the metal plug into the dielectric oxide layer.
Briefly, as an example method in accordance with the present invention:
I. Deposit FSG layer
14
by PECVD or HDP process;
II. Etch via hole
16
in FSG layer
14
;
III. Treat etched FSG layer
14
with aqueous
1. Ca(HCO
3
)
2
(source of Ca); and/or
2. Grignard reagent (RMgBr and/or RMgCl) (source of Mg) to diffuse Ca and/or Mg into FSG layer
14
forming in-situ copper barrier layer
18
;
IV. (Optional Step) Treat structure with hydrogen plasma to remove Br and/or Cl (from Grignard reagent); and
V. Deposit copper in via hole with in-situ copper barrier layer
18
and planarizing to form copper plug
20
.


REFERENCES:
patent: 4797371 (1989-01-01), Kuroda
patent: 5605858 (1997-02-01), Nishioka et al.
patent: 5696018 (1997-12-01), Summerfelt et al.
patent: 5747360 (1998-05-01), Nulman
patent: 5821168 (1998-10-01), Jain
patent: 5876798 (1999-03-01), Vassiliev

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