Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-06-03
2009-10-13
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C326S038000, C326S040000, C326S041000
Reexamination Certificate
active
07603599
ABSTRACT:
Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources are tested. Further, when it is impractical to generate a pattern from a source node S for testing a network path N to a load, subnetworks are created to perform testing. To provide the subnetworks, a source S′ is first provided close to node S that generates signal patterns to route through a path N′ to load L. When it is impractical to test a network path N from source to load L, a load L′ is further provided close to load L that receives the signal patterns from a routing path N″ provided from source S. The paths N′ and N″ overlap to cover all the routing resources of the path N.
REFERENCES:
patent: 6664808 (2003-12-01), Ling et al.
patent: 6817006 (2004-11-01), Wells et al.
patent: 6891395 (2005-05-01), Wells et al.
patent: 7000212 (2006-02-01), Agrawal et al.
patent: 7058919 (2006-06-01), Young et al.
patent: 7143384 (2006-11-01), Young et al.
patent: 7409669 (2008-08-01), Dastidar et al.
patent: 2005/0022085 (2005-01-01), Vo et al.
Mark et al., Localizing Open Interconnect Defects using Targeted Routing in FPGA's, 2004, IEEE, pp. 627-634.
Stroud et al., Built-In Self-Test of FPGA Interconnect, 1998, IEEE, pp. 404-411.
Tahoori et al., Fault Grading FPGA Interconnect Test Configurations, 2002, 608-617.
Tahoori et al., Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configurations, Feb. 2004, IEEE, vol. 23, No. 2, pp. 261-272.
Chari Madabhushi V. R.
Cossoul Matthieu P. H.
Cartier Lois D.
King John J.
Tabone, Jr. John J
Ward Thomas A.
Xilinx , Inc.
LandOfFree
Method to test routed networks does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to test routed networks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to test routed networks will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4134883