Method to strain NMOS devices while mitigating dopant...

Details Method to strain NMOS devices while mitigating dopant... Method to strain NMOS devices while mitigating dopant...

2007-05-01

2007-05-01

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000, C438S902000, C257SE21630

Reexamination Certificate

active

11060841

ABSTRACT:
The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

REFERENCES:
patent: 6165826 (2000-12-01), Chau et al.
patent: 6180454 (2001-01-01), Chang et al.
patent: 6380029 (2002-04-01), Chang et al.
patent: 6495853 (2002-12-01), Holbrook et al.
patent: 6767778 (2004-07-01), Wang et al.
patent: 7129127 (2006-10-01), Chidambaram et al.
patent: 2005/0136583 (2005-06-01), Chen et al.

Affiliated with

Also associated with

Rating

Method to strain NMOS devices while mitigating dopant... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to strain NMOS devices while mitigating dopant..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to strain NMOS devices while mitigating dopant... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3800504