Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Processing feature prior to imaging
Reexamination Certificate
2000-09-29
2002-11-26
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Processing feature prior to imaging
C430S313000, C430S317000, C430S311000, C216S040000
Reexamination Certificate
active
06485894
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to optical lithography, such as used in the fabrication of semiconductor integrated circuits, and more particularly, to methods to self-align a lithographic pattern to a semiconductor wafer without an exposure mask.
In a typical optical lithography system, optical radiation from an optical source propagates through a mask or reticle onto a photoresist layer located on the top surface of a semiconductor wafer. In this manner, the mask pattern is focused on the photoresist layer. Depending upon whether this photoresist is positive or negative, when it is subjected to a developing process the material of the photoresist is removed or remains at areas where the optical radiation was incident. Thus, the pattern of the mask is transferred to (or printed on) the photoresist. Subsequent etching processes, such as wet etching or dry plasma etching, remove selected portions of the semiconductor wafer or of layers of material located between the top surface of the wafer and the bottom surface of the photoresist layer, or of both the substrate and the layers. Portions of the substrate or of the layers of material thus are removed from the top surface of the wafer underlying areas where the photoresist was removed by the developing process but not underlying areas where the photoresist remains. Thus, the pattern of the mask is transferred to layers of material overlying the semiconductor wafer, as is desired, for example, in the art of semiconductor integrated circuit fabrication.
In fabricating such circuits, it is desirable to have as many devices per wafer as is possible. Hence, it is desirable to have as small a transistor or other feature size as possible.
A critical process step is the alignment of the mask to the semiconductor wafer for printing images on the semiconductor wafer itself or on overlying layers. Errors in the placement of one pattern with respect to another are called overlay errors. For purposes of mask alignment, each mask contains specially designed and placed registration marks which allow the alignment of a subsequent mask. The art is replete with various techniques for mask alignment so as to minimize alignment errors.
Alignment errors can be significant and can amount to as much as 50% of the minimum feature size. As device dimensions become smaller, it is desirable to eliminate mask alignment errors. In this regard, it would be advantageous to develop technology to self-align the pattern to the existing pattern on the semiconductor wafer.
Shiraishi U.S. Pat. No. 5,861,320, the disclosure of which is incorporated by reference herein, discloses an alignment mark on a semiconductor wafer having a recessed or projecting portion as a function of the wavelength used for the alignment of a mask to the semiconductor wafer.
Garofalo et al. U.S. Pat. No. 5,153,083, the disclosure of which is incorporated by reference herein, discloses a method to make a phase shifting mask by a self-aligned technique in which the first level formed, a silicon dioxide layer, serves as a phase shifting layer.
Nakata et al. U.S. Pat. No. 4,906,852, the disclosure of which is incorporated by reference herein, disclose a projection alignment method and apparatus for aligning a mask and a semiconductor wafer through optical imaging. The method and apparatus use a stepped pattern on the semiconductor wafer and a flat portion of the semiconductor wafer and an optical interference system for making the stepped and the flat portions interfere with each other.
Nakata et al. U.S. Pat. No. 4,795,261, the disclosure of which is incorporated by reference herein, disclose a reduction projection system for exposing a circuit pattern through a mask. The system has apparatus for detecting an interference pattern caused by the reflection from a mark on the semiconductor wafer and a reference mirror. The semiconductor wafer mark is under the photoresist and is stepped in the surface of the semiconductor wafer.
Makosch U.S. Pat. No. 4,779,001, the disclosure of which is incorporated by reference herein, discloses the alignment of a semiconductor wafer and a mask using an etched grating pattern on the wafer surface and a corresponding grating on the mask.
Heimer U.S. Pat. No. 4,419,013, the disclosure of which is incorporated by reference herein, discloses a mask alignment system wherein the alignment between successive masks uses alignment targets formed on the semiconductor wafer. The alignment targets on the semiconductor wafer are covered by one or more highly reflective films. To enable the target to be viewed, a phase contrast microscope is used to view the alignment target.
Imahashi U.S. Pat. No. 4,377,028, the disclosure of which is incorporated by reference herein, disclose a method and an apparatus for registering a pattern on a mask with a pattern already formed on a semiconductor wafer. There are reflector groups on the semiconductor wafer and passthrough windows on the mask. Shifting of the mask in the X-Y direction would cause the transmitted light to go from a maximum to a minimum.
None of the above references relate to the image enhancement on a semiconductor wafer by using the existing pattern on the semiconductor wafer. It would be desirable to use the existing pattern on the semiconductor wafer for image enhancement so as to be able to dispense with the use of a mask, alignment marks and all the other apparatus and equipment necessary for mask alignment.
Accordingly, it is one purpose of the present invention to have a method to create a self-aligned resist pattern by using the existing pattern on a semiconductor wafer without using a mask.
It is another purpose of the present invention to have a method to create a self-aligned resist pattern by using the existing pattern on a semiconductor wafer and the pattern of the reticle.
These and other purposes of the present invention will become more apparent after referring to the following description considered in conjunction with the accompanying Figures.
BRIEF SUMMARY OF THE INVENTION
The purposes of the invention have been achieved by providing, according to a first aspect of the invention, a method to self-align a lithographic pattern to a workpiece, the method comprising the steps of:
obtaining a workpiece having a predetermined pattern of features;
modifying at least some of the features so that when a photoresist material is applied to the pattern, there is a substantial difference in reflectivity between two adjacent features, at least one of which has been modified;
applying a photoresist material;
masklessly exposing the photoresist material;
developing said photoresist material, said substantial difference in reflectivity of said two adjacent features causing said developed photoresist material to reveal one adjacent feature but not the other.
According to a second aspect of the invention, there is provided a method to self-align a lithographic pattern to a workpiece, the method comprising the steps of:
obtaining a workpiece having a predetermined pattern of features;
modifying at least some of the features so that when a photoresist material is applied to the pattern, there is a substantial difference in reflectivity between two adjacent features, at least one of which has been modified;
applying a photoresist material;
flood exposing the photoresist material such that the area flood exposed corresponds to at least the two adjacent features in the predetermined pattern of features;
developing said photoresist material, said substantial difference in reflectivity of said two adjacent features causing said developed photoresist material to reveal one adjacent feature but not the other.
REFERENCES:
patent: 4377028 (1983-03-01), Imahashi
patent: 4379833 (1983-04-01), Canavello et al.
patent: 4419013 (1983-12-01), Heimer
patent: 4779001 (1988-10-01), Makosch
patent: 4795261 (1989-01-01), Nakata et al.
patent: 4906852 (1990-03-01), Nakata et al.
patent: 5153083 (1992-10-01), Garofalo et al.
patent: 5725903 (1998-03-01), Rostoker
patent: 5861320 (1999-01-01), Shiraishi
patent: 608
Akatsu Hiroyuki
Zach Franz X.
Blecker Ira D.
Chacko-Davis Daborah
LandOfFree
Method to self-align a lithographic pattern to a workpiece does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to self-align a lithographic pattern to a workpiece, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to self-align a lithographic pattern to a workpiece will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2994044