Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-04
2007-12-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10996074
ABSTRACT:
A method and system of selectively identifying at risk die based on location within the reticle. Reticle and stepping information is stored in a database. All reticle shots in a wafer and in a lot are overlaid on top of each other. The reticle and stepping information is used to calculate pass/fail or specific bin yield of reticle fields. It is determined if the yield of some reticle locations is below a statistical measure by a pre-determined threshold, and if so, all the die in that location are downgraded. The statistical value to compare against does not have to be based on the reticle alone. It can be a wafer of lot level statistic. The process can be applied at a lot or wafer level, or both.
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Cota Kevin
Madge Robert
Rehani Manu
LSI Corporation
Siek Vuthe
Trexler, Bushnell, Giangiorgi & Blackstone
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