Method to scale down device dimension using spacer to...

Details Method to scale down device dimension using spacer to... Method to scale down device dimension using spacer to...

2001-12-10

2002-11-19

Niebling, John F. (Department: 3738)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S300000, C438S185000

Reexamination Certificate

active

06482706

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90129019, filed Nov. 23, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method to scale down device dimension, and more particularly, to a method to scale down device dimension by confining a buried drain implantation.
2. Description of the Related Art
To obtain a short, small, light and thin device or application system, formation of buried structure such as buried drain becomes particularly popular in various memory devices. However, as the system or device is continuously shrunk, fabrication problems occur to reduce the product reliability. One of the fabrication problems is the short channel effect.
FIG. 1
shows a buried drain region formed by a conventional process. An oxide
itride/oxide (ONO) stacked layer
102
and a conductive layer
104
are sequentially formed and patterned on a substrate
100
. Using the patterned conductive layer
104
as a mask, an ion implantation process is performed to form a buried drain region
106
in the substrate
100
. As the buried drain region
106
has a dopant concentration much higher than the substrate
100
, the dopant in the buried drain region
106
diffuses outwardly to the substrate
100
to cause a reduction of the effective channel length.
In addition to the ion implantation step for forming the buried drain region, a pocket implantation step is typically performed to form a pocket doped region to avoid effects such as punch-through. Ideally, the buried drain region is within the coverage of the pocket doped region.
FIGS. 2A and 2B
illustrate the pocket doped region and the buried drain region formed by conventional process.
In
FIG. 2A
, a substrate
200
is provided. A stack layer
202
and a conductive layer
204
are formed and defined on the substrate
200
. Using a large angle tile ion implantation, a pocket doped region
210
is formed in the substrate
200
. Since the pocket doped region
210
is formed with a large tilt angle, the profile is as shown in FIG.
2
A. After the buried drain region
206
is formed in the substrate
200
, as shown in
FIG. 2B
, the buried drain region
206
is hardly covered by the pocket doped region
210
. The effect of the pocket doped region
210
is thus very limited to affect the device reliability.
SUMMARY OF THE INVENTION
The invention provides a method to scale down device dimension using a side-wall to confine buried drain implant. A substrate is provided. A first oxide layer, a nitride layer and a second oxide layer are formed on a substrate, and a conductive layer is formed on the second oxide layer. Using photolithography and etching process, the conductive layer is patterned to expose a portion of the second oxide layer. The patterned conductive layer is used as a mask layer to perform a pocket ion implantation. A pocket doped region is formed in the substrate under the exposed part of the second oxide layer.
A spacer is formed on a side-wall of the conductive layer, and the exposed part of the second oxide layer and the underlying nitride layer are removed. The formation of spacer reduces an opening defined by the patterned conductive layer. Consequently, the range to perform the drain implantation is confined. A step of ion implantation is then performed to form a buried drain region in the substrate within the pocket doped region. As the range for forming the buried drain region is reduced, so that the effective channel length is not shortened even with the diffusion of the buried drain region. This method is thus advantageous to scale down the device dimension and to obtain a higher integration.
After forming the buried drain region, a drain oxide is formed on the buried drain region as a drain oxide layer. A word line is then formed over the substrate.
The buried drain region can function as a buried bit line, while the device formed by the above method can be used to fabricate a NROM device.
In the embodiment mentioned above, the step of removing the exposed part of the second oxide layer and the underlying nitride layer can also be conducted before the spacer is formed. Thus, the spacer does not only cover the side-wall of the conductive layer, but also covers the edges of the second oxide layer and the underlying nitride layer.
In another embodiment of the invention, after the buried drain region is formed, the patterned conductive layer and the spacer on the side-wall thereof are removed. A drain oxide is then formed on the buried drain region, and a word line is formed over the substrate. Such device can be applied as a SONOS device.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 4855246 (1989-08-01), Codella et al.
patent: 5940710 (1999-08-01), Chung et al.
patent: 6297096 (2001-10-01), Boaz
patent: 6417081 (2002-07-01), Thurgate
patent: 6420237 (2002-07-01), Chang
patent: 2002/0052081 (2002-05-01), Eitan
patent: 2002/0086548 (2002-07-01), Chang

Affiliated with

Also associated with

Rating

Method to scale down device dimension using spacer to... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to scale down device dimension using spacer to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to scale down device dimension using spacer to... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2965913