Method to remove excess metal in the formation of damascene...

Details Method to remove excess metal in the formation of damascene... Method to remove excess metal in the formation of damascene...

1999-10-18

2002-04-23

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S633000, C438S636000, C438S671000

Reexamination Certificate

active

06376361

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of removing excess metal in the formation of damascene and dual damascene interconnects in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
The use of copper for interconnects in integrated circuit technology is increasing. This is primarily due to the lower resistivity of copper when compared to the more traditional aluminum. The maturation of damascene technology has allowed copper to replace aluminum in many process schemes.
Damascene approaches allow copper interconnects to be formed without etching interconnect patterns directly into the copper. Rather, the interconnect pattern is etched into the dielectric material. The copper is then deposited overlying the dielectric material and filling the trenches etched into the dielectric. Finally, an etching or a polishing operation is used to remove the excess copper so that the metal only remains in the trenches.
The last step, where the excess copper is removed, is one that can cause problems in the art. To eliminate metal shorts, it is necessary to remove all of the copper above and outside the trench boundaries. However, if too much of the copper is removed, such that the trench is no longer completely filled, other reliability problems can occur.
Referring to
FIG. 1
, a cross-section of a partially completed prior art integrated circuit device is shown. A dual damascene process, one in which both the via plug and the metal trace is filled by the same metal deposition, is illustrated. A semiconductor substrate
10
is shown. The semiconductor substrate
10
could be composed of silicon or of several microelectronic layers that incorporate both insulating and conductive materials. Conductive traces
22
are formed overlying the semiconductor substrate
10
. A dielectric layer
18
is deposited overlying the semiconductor substrate
10
. The conductive traces
22
are formed through this dielectric layer
18
as shown.
Trenches have been etched into the dielectric layer
18
. The trenches are formed to provide a connective via to the metal traces
22
. The lower, narrower part of the trenches provides this connection. The trenches also will provide the next level of conductive traces. The upper, wider part of the trenches provides the pattern for the next level of conductive traces for the integrated circuit.
A barrier layer
26
has been deposited overlying the dielectric layer
18
and lining the trenches. The barrier layer is typically composed of a material that inhibits copper diffusion. This is important because copper ions can diffuse into the dielectric layer
18
, which is typically silicon dioxide, under normal conditions and can cause reliability problems. This is a detrimental property of copper when compared to aluminum. In the prior art, the barrier layer
26
is typically composed of a combination of tantalum and tantalum nitride or a combination of titanium and titanium nitride or solely tantalum nitride.
A copper layer
30
is deposited overlying the barrier layer
26
and completely filling the trenches. A large amount of excess copper must be deposited to insure that the trenches are completely filled. This excess copper layer
30
must be removed to complete the definition of the interconnect traces. Note that, even with the large amount of excess copper, a significant valley
32
in the surface topology of the copper layer
30
occurs due to the large trenches that must be filled.
Referring now to
FIG. 2
, the excess copper layer
30
and barrier layer
26
are polished down. The typical process used is a chemical mechanical polish. Through chemical and mechanical action, this process removes the excess material from the top down. Ideally, the process is stopped by endpoint as soon as all of the excessive copper layer
30
and the barrier layer
26
are removed, that is, when the copper layer
30
and the barrier layer
26
that remain are confined to only the trenches. The resulting copper layer
30
thickness within the trenches should be the same as the thickness of the dielectric layer
18
.
In reality, it is inevitable to have copper thickness loss within the trench. This is referred to as the dishing effect. This effect is not ideal, and it can cause significant reliability problems in the circuit.
The dishing effect has two main causes. First, the barrier layer
26
materials, such as tantalum and titanium, and the dielectric layer
18
have lower polishing rates than the copper layer
30
. In addition, there is an inevitable non-uniformity of chemical mechanical polishing across the wafer. Therefore, an over-polish, beyond the detected endpoint, must be performed to ensure that the barrier layer
26
has been removed over the whole die and the whole wafer. These two factors relating to the lower polishing rate of the barrier layer
26
contribute to the significant copper thickness loss within the trenches.
Second, due the compressibility of the polishing pad used in the CMP, the valley topology
32
of the copper layer
30
top surfaces is polished away at the same time, though not necessarily the same rate, as the copper layer
30
overlying non-trench areas. Therefore, when the copper layer
30
and the barrier layer
26
in the non-trench areas are completely removed, the copper layer
30
in the trenches has been polished below the level defined by the dielectric layer
18
thickness.
Several prior art approaches disclose methods to fabricate interconnects and to planarize layers. Some of these methods use masking layers to enhance planarization. U.S. Pat. No. 4,954,459 to Avanzino et al discloses a method to planarize oxide for shallow trench isolation (STI) and interlevel dielectrics. A reverse mask of photoresist is used. The oxide is etched down where exposed by the photoresist mask. After the mask is removed, a chemical mechanical polish finishes the planarization. U.S. Pat. No. 5,792,707 to Chung teaches a process to planarize a dielectric layer where a reverse photoresist mask and a chemical mechanical polish step are used. U.S. Pat. No. 5,151,168 to Gilton et al discloses a process to create metalization patterns. A reverse image photoresist mask of the desired metal pattern is created over the wafer. The wafer is then plated to deposit the metal. U.S. Pat. No. 5,231,051 to Baldi et al teaches a process to fabricate metal contacts or vias. A metal layer is deposited overlying a dielectric layer and filling contact or via holes. The metal layer is etched down to the surface of the dielectric layer. A mask is formed overlying the via or contact plug area. A second etch is performed to remove any metal residue. The mask is then removed. U.S. Pat. No. 5,747,383 to Chen et al discloses a process to fabricate an interconnect layer where a conductive material is deposited overlying an insulating layer and filling the contact openings. The conductive material is etched down to the insulating material without over etching. A protective mask layer of magnesium oxide or silicon oxide is formed to protect the contact plugs. A second etching is performed to remove the remaining conductive material. The protective mask is removed. U.S. Pat. No. 5,578,523 to Fiordalice et al teaches a dual damascene process.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of removing excess metal in the formation of damascene and dual damascene interconnects in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to remove excess metal in the formation of damascene and dual damascene interconnects where a mask and etch sequence is used to remove a part of the excess metal in non-trench areas prior to polishing down the remaining excess metal.
In accordance with the objects of this invention, a new method of removing excess metal in the formation of an interconnect has been achieved. A semicond

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