Method to reduce via poison in low-k Cu dual damascene by...

Details Method to reduce via poison in low-k Cu dual damascene by... Method to reduce via poison in low-k Cu dual damascene by...

2000-07-12

2001-11-20

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S605000, C438S622000, C438S687000, C438S707000

Reexamination Certificate

active

06319809

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices in general, and in particular, to a method of reducing via poisoning in low-k copper dual damascene structures through ultraviolet treatment.
(2) Description of the Related Art
With the advent of ultra large scale integrated (ULSI) circuit technology, the number of interconnections required between millions of transistors have increased astronomically, as is well known to the practitioners in the art. These interconnections, in the form of metal lines, are usually are of very fine geometries and are closely spaced with respect to each other in order to conserve “real estate” in the chip on which they are formed. The planar area of the chip is further conserved by forming multi-level metallized layers separated from each other by insulative layers. The close spacing between the lines, both horizontally on the same layer, and vertically between layers, can cause higher electrical interference and cross-talk between the lines, and hence high resistance-capacitance (RC) delay for the circuitry. As the device geometries shrink further to less than 0.15 micrometers (&mgr;m), the RC delay becomes even more significant.
In order to decrease the RC delay, or, time constant, within these multi-level integrated systems, low-k (dielectric constant) insulative materials are used. Conventional semiconductor fabrication methods use silicon dioxide or similar insulative materials as both gap filler between adjacent conductor lines on the same layer and as an interlayer insulator between different layers of interconnections. Silicon dioxide has a dielectric constant of about 3.9, on a scale where 1.0 represents the dielectric constant of a vacuum. In the present manufacturing line, where materials such as black diamond, FLARE, SiLK are used in forming Cu dual damascene interconnects, low-k materials have a dielectric constant less than 3.0. However, low-k materials give rise to poisoned vias during the process of manufacturing copper dual damascene interconnects. The present invention discloses a method of preventing such poisoned vias.
Cu dual damascene is preferred as an interconnect because, as is well known in the art, copper has lower resistivity than the commonly used aluminum and, therefore contributes to lower RC delay. The damascene process also provides a better control of the metal line geometries, as described below, and therefore improves further the RC characteristics of the lines. However, if the damascene structure is not properly treated during forming of the contact and via holes, the holes can be “poisoned” due to outgassing from the insulative layers, and/or due to the hydrophobic nature of the insulative layers. A poisoned contact hole (reaching the substrate), or a poisoned via hole (connecting different metallized layers) can give rise to voids, cavities for contaminants to enter, poor interfaces between contacting conductors, and, hence, poor connections between interconnects. It is disclosed later in the embodiments of the present invention a method of treating Cu dual damascene structures in order to avoid the via poisoning problem.
Copper dual damascene process is a well-known technique for forming interconnections in semiconductor devices. It is especially well suited for Ultra Large Scale Integrated (ULSI) circuit technology where more and more devices are being packed into the same or smaller areas in a semiconductor substrate. As the feature sizes get smaller, the smaller geometries result in higher electrical resistances, which in turn degrade circuit performance. As will be described more fully later, damascene process provides a more exact dimensional control over small geometries, while copper, as the metallization material, provides better electrical characteristics.
The term ‘damascene’ is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Thus, in semiconductor manufacturing, trenches and holes in appropriate locations in the trenches are formed in an insulative material by etching, which are then filled with metal. Metal in trenches form the horizontal metal line interconnects while the metal in the underlying holes form the vertical connections to the layers of metal interconnects formed in the previous damascene structure.
Thus, in a single damascene semiconductor manufacturing process, incisions, or trenches, are formed in an insulative layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the trenches of a single damascene, hole openings are also formed at appropriate places in the trench further into the insulative layer. The resulting composite structure of trenches and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween.
In one approach for a dual damascene process shown in
FIG. 1
a
, two insulative layers (
120
) and (
130
) are formed on a substrate (
100
) with an intervening etch-stop layer (
125
). Substrate (
100
) is provided with metal layer (
110
) and a barrier layer (
115
). Metal layer can be the commonly used aluminum or copper, while the barrier can be an oxide layer. A desired trench or trench pattern (
150
) is first etched into the upper insulative material (
130
) using conventional photolithographic methods and photoresist (
140
). The etching stops on etch-stop layer (
125
). Next, a second photoresist layer (
160
) is formed over the substrate, thus filling the trench opening (
150
), and patterned with hole opening (
170
), as shown in
FIG. 1
c
. The hole pattern is then etched into the lower insulative layer (
120
) as shown in
FIG. 1
c
and photoresist removed, thus forming the dual damascene structure shown in
FIG. 1
f.
Or, the order in which the trench and the hole are formed can be reversed. Thus, the upper insulative layer (
130
) is first etched, or patterned, with hole (
170
), as shown in
FIG. 1
d
. The hole pattern is also formed into etch-stop layer (
125
). Then, the upper layer is etched to form trench (
150
) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (
120
), as shown in
FIG. 1
e
. It will be noted that the etch-stop layer stops the etching of the trench into the lower insulation layer. After the completion of the thusly formed dual damascene structure, both the hole opening and trench opening are filled with metal (
180
), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in
FIG. 1
f.
However, when trench (
150
), or hole (
170
) openings are formed through the insulative layers (
120
) and (
130
) as shown in
FIGS. 1
b
-
1
e
, moisture (
190
) is absorbed from the atmosphere by the exposed dielectric layers on the sidewalls of the openings. After copper (
180
) is deposited, moisture (
190
) is then released from the dielectric layers. This moisture diffuses into the metal causing poisoned via/contact metallurgy.
In prior art, various methods have been suggested to overcome the poisoned via problem. In U.S. Pat. No. 5,643,407, Chang teaches nitrogen plasma treatment after via etching. First, a thick insulative layer is formed over semiconductor device structures in and on a semiconductor substrate. A first metal layer is deposited over the thick insulative layer. The first metal layer is etched using conventional photolithography and etching techniques to form the desired metal pattern on the surface of the thick insulative layer. The intermetal dielectric layer is formed by first covering the patterned first metal layer with a layer of silicon oxide. The silicon oxide layer is covered with a layer of spin-on-glass material which is cured. A second layer of sili

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