Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-04-03
2007-04-03
Lindsay, Jr., Walter L. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S303000, C257SE21092, C257SE21115
Reexamination Certificate
active
10620492
ABSTRACT:
The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.
REFERENCES:
patent: 5397909 (1995-03-01), Moslehi
patent: 5998289 (1999-12-01), Sagnes
patent: 6541320 (2003-04-01), Brown et al.
patent: 6686637 (2004-02-01), Dokumaci et al.
patent: 2002/0048918 (2002-04-01), Grider et al.
patent: 2003/0032225 (2003-02-01), Brown et al.
Mansoori Majid Movahed
Pacheco Rotondaro Antonio Luis
Smith Brian Ashley
Tsao Alwin
Brady III W. James
Garner Jacqueline J.
Lindsay Jr. Walter L.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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