Method to reduce the node contact resistance

Details Method to reduce the node contact resistance Method to reduce the node contact resistance

1999-11-22

2002-06-04

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S656000, C438S964000

Reexamination Certificate

active

06399440

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a method for reducing the resistance of the node contact, particularly relates to a method of eliminating an interface layer between a conductive plug and a hemispherical silicon grain layer.
BACKGROUND OF THE INVENTION
As the semiconductor memory device becomes more highly integrated, the area occupied by a capacitor of a DRAM storage cell typically shrinks and it will cause the capacitance reduce of the capacitor. Owing to the leakage current, however, it is necessary to refresh the capacitor continuously in order to keep the stored state, especially when the capacitance of the capacitor is limited. Furthermore, the area reduction of the capacitor occupied will cause the capacitor to be disturbed by the alpha particle more easily.
Until now, there has been much effort directed to keep a relatively large capacitance of the capacitors in order to achieve a high signal-to-noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference) as the memory device becomes highly integrated. As the followings, there are some approaches to increase the storage capability of the capacitor while the area occupied by the capacitor maintains small enough. (1) substituting a high capacitance material for traditional material to increase the storage charges per unit area of the capacitor, for example: the substitution the of Ta
2
O
5
and TiO
2
for SiO
2
. (2) decreasing the dielectric layer thickness of the capacitor: because of the Fowler-Nordheimn tunneling effect, the dielectric layer thickness is limited to a minimum value and one can not improve the capacitor too much by this method. (3) variation the shape of the capacitor electrodes: the capacitor may have protrusions, cavities, etc., to increase the surface area of the capacitor electrode. (4) increasing the contact area between the conductive layer implementing the electrode of the capacitor and the dielectric layer: the surface between the dielectric layer and the conductive layer can be varied to a ragged type surface and not be even a plain surface anymore.
The aforementioned third approach, it has been widely used and a crown-shaped or an U-shaped capacitor has been developed. For the last one method, one type of the surface variation is a ragged polysilicon layer. The combination implementing these two methods is as following description.
Referring
FIG. 1
, a polysilicon layer
12
is formed in the dielectric layer
15
which has been deposited on the substrate
10
. Then, a dielectric layer
14
is deposited and an opening
18
is created by etching process with well-known lithography. After the etching process, a thin oxide layer
16
will exist usually on the bottom surface of the opening
18
. Referring
FIG. 2
, a polysilicon layer
13
is deposited on the dielectric layer
14
and then a hemispherical silicon grain (HSG) layer
11
is formed on the polysilicon layer
13
. Forming a dielectric layer
18
on the HSG layer
11
is followed by forming a conductive layer
17
on the dielectric layer
18
.
Although combination of the crown-shaped capacitor and the ragged polysilicon layer effectively reduces the contact resistance, the existing of the native oxide layer
16
actually increases the contact resistance. The high contact resistance of the capacitor will lower the effectiveness of the memory cell, for example the program current is high (the lowest limit current to write a signal into the memory), the read current is low (the signal read from the memory) and the program speed is slow.
Therefore, it is really required to reduce the native oxide layer as little as possible and thereby all the high cell integration, the effective operation and reliable operation could be achieved simultaneously.
SUMMARY OF THE INVENTION
The present invention provides a manufacturing process for reducing contact resistance.
Another object of the present invention is to provide a method for eliminating an interface layer between a poly plug and a hemispherical silicon grain.
In the present invention, a substrate comprising a conductive plug and a storage node opening is provided, and the storage node opening is located on the conductive plug. Then, a first conductive layer with a thickness between about 500 to 1000 angstroms is formed conformably over the inside surface of the storage node opening. Next, a hemispherical silicon grain layer with a thickness range from about 300 to 600 angstroms is formed on the first conductive layer.
The hemispherical silicon grain layer and the first conductive layer above the surface of the conductive plug is implanted with phosphorus, the dose is about 1E15 to 1E16 atoms/cm
2
. The grains at the interface layer between hemispherical silicon grain and conductive plug become amorphous due to the bombardment of the implanted impurities. The substrate is annealed in the temperature range from about 800 to 1000° C., and the interface atoms are re-crystallized in the annealing process. The re-crystallization of the interface layer can greatly reduce the resistance of the node contact. Finally, a dielectric layer is deposited on the hemispherical silicon grain and a second conductive layer, as another electrode of the capacitor, is formed on the dielectric layer.


REFERENCES:
patent: 6165830 (2000-12-01), Lin et al.

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