Method to reduce the depth of a buried contact trench by using a

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438532, 438381, 438586, 438647, 438649, 257344, 257754, 257382, 257385, 257756, H01L 218244, H01L 2904

Patent

active

060016817

ABSTRACT:
A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.

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