Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-01-27
2001-10-23
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S296000, C438S433000, C438S262000, C438S526000, C438S640000, C438S700000
Reexamination Certificate
active
06306737
ABSTRACT:
CROSS-REFERENCE TO RELATED PATENT/PATENT APPLICATIONS
The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
U.S. Pat. No./Ser. No.
Filing Date
TI Case No.
60/068,543
12/23/97
TI-23167
FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and more particularly to an improved method of fabricating a source line in flash memory having shallow trench isolation (STI) structures.
BACKGROUND OF THE INVENTION
Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are typically constructed from various microelectronic devices fabricated on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a pattern of conductor, semiconductor, and insulator regions formed on the semiconductor substrate.
The density of the microelectronic devices on the semiconductor substrate may be increased by decreasing spacing between each of the various semiconductor devices. The decrease in spacing allows a larger number of such microelectronic devices to be formed on the semiconductor substrate. As a result, the computing power and speed of the semiconductor component may be greatly improved.
FLASH memory, also known as FLASH EPROM or FLASH EEPROM, is a semiconductor component that is formed from an array of memory cells with each cell having a floating gate transistor. Data can be written to each cell within the array, but the data is erased in blocks of cells. Each cell is a floating gate transistor having a source, drain, floating gate, and a control gate. The floating gate uses channel hot electrons for writing from the drain and uses Fowler-Nordheim tunneling for erasure from the source. The sources of each floating gate in each cell in a row of the array are connected to form a source line.
The floating gate transistors are electrically isolated from one another by an isolation structure. One type of isolation structure used is a LOCal Oxidation of Silicon (LOCOS) structure. LOCOS structures are generally formed by thermally growing a localized oxidation layer between the cells to electrically isolate the cells. One problem with the LOCOS structure is that the structure includes non-functional areas that waste valuable space on the semiconductor substrate.
Another type of isolation structure used is a Shallow Trench Isolation (STI). STI structures are generally formed by etching a trench between the cells and filling the trench with a suitable dielectric material. STI structures are smaller than LOCOS structures and allow the cells to be spaced closer together to increase the density of cells in the array. However, STI structures are often not used in FLASH memory due to the difficulty in forming the source line that connects the cells in each row. The source line in FLASH memory utilizing STI structures often has a higher resistance than a corresponding FLASH memory that uses LOCOS structures. The increased electrical resistance reduces the operational performance of the memory.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an improved source line for flash memory using an STI structure and method of construction. The present invention provides an improved source line for flash memory using an STI structure and method of construction that substantially eliminates or reduces problems associated with the prior methods and systems.
An embodiment of the instant invention is a method of forming an electronic device having a conducting line, the method comprising the steps of: forming trenches in a semiconductor layer, the trenches having a top, a bottom, sidewalls, and filled with a dielectric material; forming a plurality of steps in said sidewalls of said trenches; and providing a dopant into said steps of said sidewalls of said trenches. Preferably, the method of forming the plurality of steps in the sidewalls of the trenches further comprises the steps of; etching said dielectric material, thereby exposing a portion of said sidewalls; oxidizing said portion of said sidewalls, thereby growing an oxide on said portion of said sidewalls; and etching said oxide on said portion of said sidewalls and said dielectric material. Prefeerably the oxidizing step comprises exposing the portion of the sidewalls to an oxygen or oxygen containing species in the presence of a plasma.
An advantage of the invention is reduced source line resistance compared with other methods. Other technical advantages will be readily apparent to one. skilled in the art from the following FIGUREs, description, and claims.
REFERENCES:
patent: 4744858 (1988-05-01), McDavid et al.
patent: 4902377 (1990-02-01), Berglund et al.
patent: 5663091 (1997-09-01), Yen et al.
patent: 5874346 (1999-02-01), Fulford, Jr. et al.
patent: 6130454 (2000-10-01), Gardner et al.
Ambrose Thomas M.
Mehrad Freidoon
Tsung Lancy Y.
Brady III W. James
Lytle Craig P.
McLarty Peter K.
Smith Matthew
Telecky , Jr. Frederick J.
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