Method to reduce power consumption within a clock gated...

Details Method to reduce power consumption within a clock gated... Method to reduce power consumption within a clock gated...

2007-09-06

2009-12-29

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S033000, C327S544000, C713S310000

Reexamination Certificate

active

07639046

ABSTRACT:
A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of:deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation,propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.

REFERENCES:
patent: 2003/0131270 (2003-07-01), Abernathy et al.
Li, et al. Deterministic Clock Gating for Microprocessor Power Reduction, ECE Department, Purdue University.

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