Method to reduce plasma etch fluting

Details Method to reduce plasma etch fluting Method to reduce plasma etch fluting

1999-10-07

2001-10-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S942000

Reexamination Certificate

active

06303416

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the etching of patterns on a semiconductor substrate and more specifically to a method and process to reduce plasma etch fluting during the etching of a pattern on a semiconductor substrate.
2. Description of Related Art
Modem oxide plasma etches based on fluorocarbon feed gases have a tendency to create fluted or scalloped profiles. Fluting is the creation of vertical sidewall irregularities during plasma etching, also referred to as striations, scalloping or sidewall roughness. The problem with the present art is that during etching, the pattern of the modified resist structure that is adjacent to the substrate is directly transferred into the surface of the substrate. The origin of the fluting appears to be a change in the structure of the resist mask during the etch by a combination of either polymer deposition or selective erosion. Fluting creates a number of problems including rough sidewalls, metallized ceramic to metallized ceramic shorts associated with rough tungsten fill and other defects. Fluting dimensions on the order of 20 to 50 nm are particularly problematic as substrate feature dimensions approach the sub 0.2 &mgr;m regime.
Fluting is observed in many etches and different resist systems, especially when the etch contains feed gases that tend to form polymer precursors such as CF
4
, CHF
3
, or C
4
F
8
.
In metallized ceramic (“MC”) and contact hole processes, it has been found that a carbon rich chemistry (fluorocarbon) is needed for high selectivity of the oxide etch. Polymerizing etch chemistries, such as fluorocarbon etching, produce the worst fluting while non-polymerizing gases like O
2
, SF
6
, and NF
3
, produce the least amount of fluting.
Fluting is also observed with both positive and negative resists. Exposure dose does not appear to affect the extent of fluting, while focus is shown to have an effect.
The thickness of the resist, relative to the thickness of the substrate, has an impact on fluting. The more resist remaining post-etch typically correlates to less fluting. Anti-reflective coatings (“ARC”) and mainly ARC open etch and etch chemistries also have an effect on fluting.
Attempts to reduce fluting have included increasing the resist thickness, although, in metallized ceramic, a resist thickness of 7000 to 9000 angstroms did not have an effect for the typical 6500 angstrom etched MC depth. A drawback to increasing the resist thickness is that it will restrict resolution capability as one moves to smaller dimensions on the substrate and will also increase the aspect ratio of resist height to width to greater than 3:1.
Another method to reduce fluting is to optimize etch chemistries, such as by adding O
2
. This method reduces fluting but also reduces oxide etch selectivity. The use of SF
6
and NF
3
, gases, which are non-polymerizing, can reduce fluting, but they also reduce etch selectivity.
The use of ultraviolet (“UV”) light in post development treatment can be used to harden the resist and helps decrease resist erosion by densification of the resist film. This method works better for I-line resists. Chemically amplified films (e.g., DUV resists) tend to shrink upon UV hardening. However, UV hardening, while decreasing resist erosion, has not been shown to reduce fluting.
Other methods of reducing sidewall roughness during dry etching include the choice of dielectric etch chemistry, modification of the initial resist processing and deposition of an SiN sidewall, flood exposure of the initial photoresist mask and optimization of the postbake temperature. Some of the drawbacks of these processes include: added process costs, a reduced process window, are usable only for certain processes or are only marginally effective.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and process to reduce fluting during the etching of a resist pattern on a semiconductor substrate.
It is another object of the present invention to provide a method and process to reduce fluting during the etching of a pattern on a semiconductor substrate that does not restrict resolution capability.
A further object of the invention is to provide a method and process to reduce fluting during the etching of a pattern o n a semiconductor substrate that does not limit oxide etch selectivity.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will b e apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of forming a resist pattern t o reduce fluting on a substrate during an etching process. The method comprises the steps of applying a layer of a resist material, the resist layer having an upper portion and a lower portion, on a surface of the substrate. The resist layer and substrate is then heated and exposed to light to expose the upper and lower portions of the resist layer. The exposed resist layer is heated and then developed to form the resist pattern, the resist pattern having a lower portion in contact with the substrate, the lower portion having a width which is narrower than the upper portion of the resist pattern, the upper portion of the resist pattern shadowing a portion of the substrate adjacent the lower portion from the direction of a primary etch. In the preferred embodiment, during the exposure a focus setting is used which corresponds to a negative focus shift. Preferably, the upper portion of the resist layer has a first dissolution rate and the lower portion of the resist layer has a second dissolution rate. In the preferred embodiment the resist layer includes a thermally labile material whereby after the heating of the resist layer and substrate, the first dissolution rate is different from the second dissolution rate. It is preferred that during the exposure step, the lower portion of the resist layer receives less light than the upper portion.
The method also includes the step, between the steps of heating the resist layer and substrate, and exposing the resist layer, of depositing a layer of a second resist material over the resist layer, wherein the resist layer has a higher dissolution rate than the second resist layer. The resist layer and second resist layer and substrate are then heated.
The preferred method also comprises the step, prior to the step of applying a layer of a resist on a surface of the substrate, of coating the substrate surface with an underlayer material. It is preferred that the underlayer material is applied by spin-coating, chemical vapor deposition or evaporation. It is also preferred that the underlayer material be capable of exhibiting a chemical interaction with the resist layer. In the preferred embodiment the underlayer material is an anti-reflective material. In the most preferred embodiment the underlayer material is selected from the group consisting of TiN, silicon nitride, silicon oxynitride, TEOS and organic ARC. It is also preferred that the underlayer material comprise a partially soluble material, such as a photoresist resin, which is partially dissolved during the developing of the resist layer. The method also comprises the step, after the step of developing the resist layer, of partially dissolving the underlayer using a solvent.
In another aspect, the present invention comprises a process for manufacturing a semiconductor device using a resist pattern that reduces fluting during an etching process. The process comprises the steps of applying a resist structure on a substrate to be patterned, a lower portion of the resist structure being in contact with the substrate, forming an undercut on the resist structure such that the lower portion of the resist structure has a width that is narrower than an upper portion of the resist structure, the undercut forming a region on the substrate shadowed from a primary

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