Method to reduce parasitic capacitance of MOS transistors

Details Method to reduce parasitic capacitance of MOS transistors Method to reduce parasitic capacitance of MOS transistors

2001-12-20

2004-03-30

Nguyen, Van Thu (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S230000, C438S696000

Reexamination Certificate

active

06713357

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance, and to MOS transistors obtained thereby. The method has particular utility in the manufacture of high speed integrated circuit (IC) semiconductor devices.
BACKGROUND OF THE INVENTION
The escalating requirements for high integration density and performance associated with ultra-large scale (“ULSI”) integration semiconductor devices are difficult to satisfy in terms of providing high circuit speeds. The circuit speed of such integrated circuit (“IC”) devices varies inversely with the product of the resistance and capacitance, i.e., the “RC product” of the component transistors and the interconnection system. Thus, the greater the value of the RC product, the more limited the circuit speed. As a consequence of the RC effect, the rejection rate of IC devices due to circuit speed delays has become a limiting factor in IC fabrication.
According to current methodology for fabrication of IC devices utilizing multi-level metallization patterns, at least one dielectric layer, e.g., a gap-fill layer, is formed to cover the transistors and the surface of the semiconductor substrate in or on which the transistors, e.g., MOS transistors, are formed. However, a consequence of having a structure wherein multiple conductive layers are separated by a layer of a dielectric material is the formation of parasitic capacitances, e.g., between the conductive gates of the MOS transistors and the source/drain regions. The parasitic capacitance between the conductive materials, layers, or regions separated by insulating material, e.g., sidewall spacer and/or gap-fill materials, contributes to the RC product, hence time delay or operating speed, of microelectronic devices.
The capacitance of the parasitic capacitor between the gate electrode and source/drain regions of MOS transistors is related to the particular insulating materials present therebetween, typically the sidewall spacer and gap-fill dielectrics. A typical gap-fill dielectric material is silicon dioxide (SiO
2
) and typical dielectric materials utilized for the spacers formed on opposite sidewalls of the gate electrode are SiO
2
and silicon nitride (Si
3
N
4
). However, the dielectric constants, k, for these materials are quite high, i.e., about 3.9 for SiO
2
and 7.0 for Si
3
N
4
. (For purposes of this disclosure, materials with k values above about 3.9 are considered as “high-k” materials and materials with k values below about 3.9 are considered as “low-k” materials). As a consequence of the presence of such high-k materials in the form of sidewall spacers and/or gap-fill, the parasitic capacitance between the gate electrodes and source/drain regions of MOS transistors and similar devices utilizing such dielectrics is significantly high and, conversely, the device operating speeds are lowered.
In view of the foregoing, there exists a need for methodology enabling the formation of microelectronic devices, e.g., MOS transistors and MOS transistor-based devices, such as CMOS devices, which enables a substantial and significant reduction in parasitic capacitance between the gate electrodes and source/drain regions of the MOS transistors, whereby the RC time delay is decreased and operating speeds of the devices are increased.
The present invention, wherein thin, L-shaped dielectric spacers are formed on respective opposing side surfaces of a gate electrode/gate oxide layer stack, and the resultant structure subsequently covered with a low-k dielectric material, e.g., a gap-fill material, effectively addresses and solves the problem of parasitic capacitance associated with high-k dielectric sidewall spacers of conventional configuration, while maintaining full capability with all other aspects of conventional techniques for automated manufacture of microelectronic devices such as IC devices. Further, the methodology provided by the present invention can be readily and easily implemented in cost-effective manner utilizing conventional layer deposition and removal techniques. Finally, the methodology afforded by the present invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method for manufacturing a semiconductor device having reduced parasitic capacitance.
Another advantage of the present invention is a method for manufacturing an improved MOS transistor device having reduced parasitic capacitance.
Yet another advantage of the present invention is an improved semiconductor device having reduced parasitic capacitance.
Still another advantage of the present invention is an improved MOS transistor device having reduced parasitic capacitance.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device having reduced parasitic capacitance, comprising sequential steps of:
(a) providing a semiconductor substrate including a surface with at least one MOS transistor structure therein or thereon, including a spaced-apart pair of shallow depth source and drain regions and an electrically conductive gate electrode having first and second opposing side surfaces and a top surface;
(b) forming a thin, L-shaped sidewall spacer of a high dielectric constant (high-k) insulator material on each of the first and second opposing side surfaces of the gate electrode, each thin, L-shaped sidewall spacer having a vertical portion extending on a respective side surface of the gate electrode to the top surface of the gate electrode and a horizontal portion extending on the substrate surface for a selected distance; and
(c) forming a layer of a low dielectric constant (low-k) insulator material over at least the vertical and horizontal portions of each of the thin, L-shaped sidewall spacers, whereby parasitic capacitance between the gate electrode and each of the source and drain regions is reduced.
In accordance with embodiments of the present invention, step (a) comprises providing a semiconductor substrate of first conductivity type, including:
(i) a thin gate insulator layer in overlying contact with at least a portion of the substrate surface;
(ii) an electrically conductive gate electrode in overlying contact with the thin gate insulator layer, the gate electrode comprising first and second opposing side surfaces- and a top surface;
(iii) a pair of spaced-apart, shallow-depth, lightly-doped source and drain regions, each of the source and drain regions extending in the substrate to just beneath a respective proximal edge of the gate electrode; and
(iv) a thin conformal liner layer in overlying contact with the substrate surface and the first and second opposing side surfaces and top surface of the gate electrode.
According to certain embodiments of the present invention, step (a) comprises providing a silicon (Si) substrate; the thin gate insulator layer (i) comprises a silicon oxide layer or a nitride/oxide layer stack; the electrically conductive gate electrode (ii) comprises polysilicon; and the thin conformal liner layer (iv) comprises a silicon oxide.
In accordance with embodiments of the present invention, step (b) comprises forming the thin, L-shaped sidewall spacer on each of the first and second opposing side surfaces of the gate electrode by sequential steps of:
(b
1
) forming a relatively thin, conformal layer of the high-k insulator material extending over the substrate surface and the first and second opposing side surfaces and top surface of the gate electrode;
(b
2
) forming a relatively

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