Method to reduce inverse-narrow-width effect

Details Method to reduce inverse-narrow-width effect Method to reduce inverse-narrow-width effect

1999-11-12

2001-08-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S524000

Reexamination Certificate

active

06277697

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a fabrication method for an integrated circuit. More particularly, the invention relates to a fabrication method for an integrated circuit comprising a shallow trench isolation (STI) structure.
2. Description of the Related Art
In the fabrication of an integrated circuit comprising a shallow trench isolation structure, the oxide layer filling the shallow trench is damaged and forms a recess at the top edge corner of the trench during the removal of the pad oxide layer on the active region. The polysilicon, during its formation to become a gate, fills the recess. The top edge corner of the shallow trench isolation structure, as a result, is covered by the polysilicon, in which a local intensified field is induced, causing the transistor to have a lower threshold voltage in the area next to the shallow trench isolation structure and leading to an increase of the sub-threshold leakage of the transistor. As the line-width of an integrated circuit continues to be reduced, the effect of the local intensified field on the threshold voltage of a transistor becomes more significant. Since this phenomenon is opposite to the narrow-width-effect in which the threshold voltage increases with a reduction of the line width, it is therefore known as the inverse-narrow-width-effect.
In the conventional approach to reduce the inverse-narrow-width-effect. boron ions are implanted in the inner wall of the shallow trench to form a boron-doped region in the substrate along the shallow trench. The boron implantation is conducted after the formation of the trench and before the filling of the shallow trench with the oxide layer. The influence on the threshold voltage of a transistor by the local intensified field, because the top edge corner of the isolation structure is covered by polysilicon, is hence prevented. The boron doped region, formed according to the conventional approach, is distributed throughout the entire shallow trench sidewall and the substrate at the bottom of the trench. As a result, the P-N junction, formed by the connection of the boron-doped region and the source/drain region of the transistor, is in contact with the substrate. When the transistor is operating, the voltage applied to the transistor causes the P-N junction to generate a very high junction leakage in the substrate, seriously deteriorating the quality of the transistor. Especially in the dynamic random access memory (DRAM) cell structure, the junction leakage and the sub-threshold leakage due to the inverse-narrow-width-effect induce a serious drainage of the charge stored in the memory cell and greatly increase the frequency of the refresh cycle.
SUMMARY OF THE INVENTION
In the light of the foregoing, the present invention provides a method to effectively reduce the inverse-narrow-width-effect, in which the effect of the local intensified field on the threshold voltage at the edge of the shallow trench isolation structure is reduced. The problem of a junction leakage because of the P-N junction being in contact with the substrate is also prevented.
The present invention provides a method to effectively reduce the inverse-narrow-width-effect, in which a semiconductor substrate, covered by a pad oxide layer, is provided. A nitride layer and a cap oxide layer are sequentially formed to cover the pad oxide layer. Photolithography and etching is further conducted to remove a portion of the cap oxide layer and the nitride layer to define the active region and the isolation region. The cap layer formed by the nitride layer and the cap oxide layer covers the pad oxide layer on the active region. The pad oxide layer in the isolation region, however, is exposed. Using the cap layer as a mask, a doping process is conducted in which boron ions are implanted in the substrate to form a doped region adjacent to the upper surface of the substrate. The area of the doped region is formed, by means of tilt implantation, at the edge of the active region and in the substrate of the isolation region. The depth of the doped region is less than the depth of the source/drain region formed subsequently. Thereafter, a portion of the pad oxide layer, the doped region located in the isolation region and the underlying substrate are removed to form a shallow trench in the isolation region adjacent to the active region. Since the area of the doped region includes not only the isolation region, it also includes the edge of the active region. As a result, the substrate at the edge of the active region still comprises a portion of the doped region after the formation of the shallow trench. A liner oxide layer is further formed to cover the inner walls of the shallow trench. An oxide layer, which has the same height as the upper surface of the cap layer, is also formed to fill the shallow trench. The pad oxide layer and the cap layer in the active region are then removed by wet etching to expose the substrate in the active region. Thereafter, a gate oxide layer and a gate are formed on the substrate in the active region.
According to the above approach, removing the pad oxide layer and the cap layer in the active region by wet etching to expose the substrate in the active region may also form a recess at the top edge corner of the shallow trench, leading to the formation of a thicker gate. Since the doped region in the substrate at the edge of the active region can prevent the influence of the local intensified field on the threshold voltage of the transistor, the inverse-narrow-width-effect is thereby mitigated.
In addition, the depth of the doped region formed according to the present invention is shallower than the depth of the source/drain region, the P-N junction formed between the doped region and the source/drain region is therefore not in contact with the substrate. The junction leakage is therefore effectively reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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