Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-12-20
2001-06-05
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S637000, C438S677000, C438S756000
Reexamination Certificate
active
06242331
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method for semiconductor manufacturing and more specifically the cleaning of the surface of a semiconductor device prior to the deposition of the contact metallization layer, and particularly, to a method utilizing a hydrogen peroxide cleaning treatment to remove traces of contaminants in the metal contact area prior to the deposition of the contact metal.
(2) Description of Prior Art
As circuit density and therefore device density increases, metal contact dimensions have to be decreased accordingly to minimize the contact area as part of the total chip area. Contact resistance is normally inverse to contact size, that is the smaller the contact size, the higher the contact resistance. This makes contact resistance a significant and sometimes dominant factor in very large scale integration (VLSI) metal system performance. Therefore an important element in the manufacturing and subsequent operation of integrated circuit devices is the electrical contacts and associated contact resistance which are required to conduct the power and signals throughout the integrated circuitry.
For example, for a typical metal oxide semiconductor field effect transistor (MOSFET), these contacts are fabricated through the standard lithographic process utilizing photoresist with optical masks to pattern the contact areas. As illustrated in
FIG. 1
, a cross section of two typical FET devices are shown. A thin silicon dioxide layer (SiO
2
)
12
typically between 80 and 150 Å thick is placed on a substrate
10
as a gate oxide dielectric. This is normally followed by a deposition of polysilicon
14
A to a nominal thickness of 3150 Å for the gate control voltage electrode, followed by a tetraethyl orthosilicate (TEOS) oxide layer
16
A nominally 3000 Å thick for gate insulation and spacer isolation. After patterning and a TEOS and poly etching processes, a thin layer of silicon nitride (SIN)
22
is deposited to a nominal thickness of 300 Å over the TEOS layer
16
A followed by a final contact passivation dielectric of boron phosphorous silicon glass (BPSG)
24
to a nominal thickness of 3000 Å. The structure is subsequently patterned with photoresist (PR)
26
and the contact hole
30
A is opened with a wet isotropic etch to produce the structure shape depicted in
FIG. 1
in preparation for contact metallization. This contact hole requires a cleaning process that assures good metal contact and subsequent low contact resistance. The final contact opening process is typically a dry etch cleaning step using a gas containing fluorine. This etch is typically followed by a nominal 2 minute buffered oxide etch (BOE) wet dip cleaning step prior to contact metal sputtering. As contact hole dimension is reduced from 2 um to 1 um, this BOE premetal dip does not always remove a fluoride residue left from the dry etch process. Since fluorine acts as a donor element, this residue can affect the contact resistance for a P+ to metal contact. This perturbation in contact resistance can effect device performance and impact process yields for small contact hole devices. It is desired to define a method for improving contact cleaning prior to metal deposition thereby improving the metal contact ohmic resistance maintaining or improving device performance and process yields. U.S. Pat. No. 4,752,505 to Arac teaches a pre-metal deposition clean for B—Si—O insulating layer. U.S. Pat. No. 5,486,266 to Tsia et al shows a method of cleaning a silicon contact surface using H
2
O
2
. U.S. Pat. No. 5,229,334 to Kato shows a method of forming a gate insulating layer by cleaning using H
2
O
2
. U.S. Pat. No.5,308,400 to Chen shows a wafer cleaning process using H
2
O
2
. U.S. Pat. No. 5,670,019 to Huang shows a H
2
O
2
cleaning process for removing precipitates after a tungsten etchback process. U.S. Pat. No. 5,801,096 to Lee et al shows a method of forming contact holes and filling the holes with metal.
SUMMARY OF THE INVENTION
Accordingly, it is the primary objective of the invention to provide an effective and manufacturable method for cleaning the surface of a partially manufactured integrated circuit so that a subsequently deposited metal film will adhere well to the surface and have a well controlled contact resistance, thereby enhancing device yield and performance.
Furthermore, it is the objective of the invention to maintain or improve contact resistance while maintaining important device characteristics such as effective channel length (Leff) and device threshold voltage (Vtp).
Yet another object of the invention is to reduce or maintain the contact resistance and the range thereof, as the contact hole dimensions are reduced below 2.0 um to a nominal 1.0 um size range.
Another objective of the invention is to simplify the process by eliminating an insulating or passivation layer, while maintaining appropriate insulating, isolation and dielectric properties.
A separate aspect of this invention is to improve gate polysilicon passivation by using a single layer of 5K Å TEOS, or alternatively, using a single layer of 5 to 6K Å BPSG.
The above objectives are achieved by the methods of the invention which describes a process for developing a semiconductor device low resistance electrical contact. In this process a gate oxide layer followed by a polysilicon layer is deposited on the semiconductor substrate in proximity to the device contact area. It is subsequently patterned with photoresist and etched to produce the desired gate structure. This is followed by a deposited layer of silicon dioxide or silicon nitride (SIN) which is appropriately patterned and etched to form gate isolation spacers. Then a nominal 300 Å layer of silicon nitride (SIN) is deposited followed by a layer of tetraethyl orthosilicate (TEOS) or borophosphosilicate glass (BPSG). The contact area is defined by photolithography, and the passivation layers are etched either by a dry etch such as a RIE process, or a combination of a wet BOE process followed by a dry etch, to form the metal contact holes. Prior to sputtering the contact metal, the contact area is cleaned with a dip in a BEO solution, followed by a key aspect of the invention process, a Hydrogen Peroxide (H
2
O
2
) dip. This H
2
O
2
cleaning step enables lower device contact resistance for the P+ contact areas which is essential to good device performance. It has the additional benefit of maintaining or enhancing product yield as the contact hole size is decreased to meet the requirements of ever larger scale device integration.
REFERENCES:
patent: 4752505 (1988-06-01), Arac
patent: 5229334 (1993-07-01), Kato
patent: 5308400 (1994-05-01), Chen
patent: 5486266 (1996-01-01), Tsai et al.
patent: 5626716 (1997-05-01), Bosch et al.
patent: 5670019 (1997-09-01), Huang
patent: 5801096 (1998-09-01), Lee et al.
patent: 5885865 (1999-03-01), Liang et al.
patent: 5885895 (1999-03-01), Liu et al.
patent: 5908509 (1999-06-01), Olesen et al.
patent: 5939333 (1999-08-01), Hurley et al.
patent: 5972123 (1999-10-01), Verhaverbeke
patent: 6046103 (2000-04-01), Thei et al.
Chang Chai-Der
Chu Cheng-Yu
Liao Chi-Hung
Tseng Te-Fu
Ackerma Stephen B.
Quach T. N.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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