Method to produce localized halo for MOS transistor

Details Method to produce localized halo for MOS transistor Method to produce localized halo for MOS transistor

2002-10-11

2004-06-01

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S524000

Reexamination Certificate

active

06743684

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly to methods for forming localized halo structures in a semiconductor substrate in the fabrication of semiconductor devices.
BACKGROUND OF THE INVENTION
Several trends exist presently in the semiconductor device fabrication industry and the electronics industry. Devices are continually getting smaller, faster and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and speed. In light of all these trends, there is a need in the industry to provide smaller and faster MOS transistors used to provide the core functionality of the integrated circuits used in these semiconductor devices.
The phenomenal success of the MOS transistor has been partially due to the capability of the MOS transistor to take advantage of the lateral scaling improvements in the technologies. Lateral scaling results in simultaneous improvements in both the performance and the packing density of the devices. Although generalized scaling has served well for the last few decades, many of the technology advances that allow the devices to continue improving the performance and the packing density are approaching fundamental physical limitations. Future device improvements will require the devices to be either optimized for voltage reduction, high performance, or reliability.
Gate oxide thickness, junction scaling, and well engineering in MOS devices has enabled channel length scaling by improving short channel characteristics. By changing the doping profile in the channel region, the distribution of the electric field and potential contours can be changed. The goal is to optimize the channel profile to minimize the off-state leakage while maximizing the linear and saturation drive currents. Channel doping optimization can improve the circuit gate delay, for example, by about 10% for a given technology. Super Steep Retrograde Wells (SSRW) and halo implants (or pocket implants) have been used as a means to scale the channel length and increase the transistor drive current without causing an increase in the off-state leakage current.
Retrograde well engineering changes the 1-D characteristics of the well profile by creating a retrograde profile (the subsurface concentration is higher than the surface concentration) toward the Si/SiO
2
surface of a MOS device. The halo architecture creates a localized 2-D dopant distribution near the S/D regions and extends under the channel. Halos are generally known for their ability to stop unwanted source/drain leakage conduction, or punchthrough current, and as such, are sometimes referred to as a “punchthrough stopper”.
The retrograde well profile has been used to improve device performance and is typically created by using a slow diffusing dopant species such as arsenic or antimony for PMOS devices and indium for NMOS devices. Retrograde wells may only slightly improve saturated drive currents relative to uniform wells, but with today's deep sub-micron technologies, significantly improve linear drive currents and lead to improved circuit performance.
Additional benefits and improvements attributable to a theoretically ideal halo with optimal retrograde dopant profiles will be discussed in association with FIG.
1
.
FIG. 1
illustrates a 2-D simulation
1
of a true localized and optimal halo profile together with a potential profile for a MOS transistor. The MOS transistor comprises a gate
2
having a channel length
2
a
, a gate-oxide
3
having a thickness t
ox
3
a
, and a semiconductor substrate
4
with source/drain regions having a depth
4
a
on either side of a channel region.
Several graded profiles are illustrated within a channel portion of the semiconductor substrate
4
, exhibited by a generally vertically retrograde profile
5
a
, a generally laterally graded profile toward the center of the channel
5
b
, and a generally diagonally graded profile toward the source/drain regions
5
c
. Implanted dopant concentrations symbolized by solid lines
6
-
13
, range from a high concentration p-type dopant 6, thru a zero dopant concentration 9, to a high concentration n-type dopant 13 to produce the retrograde profiles
5
a
,
5
b
, and
5
c
. The centers of highest p-type dopant concentration 6, each form the center of the optimal halo.
In the MOS transistor of
FIG. 1
, a dopant concentration profile below the surface channel is preferably a vertically retrograde profile
5
a
toward the substrate surface to provide for high carrier mobility close to the surface under the gate. Since dopant impurities scatter mobility carriers and degrade linear drive current, ideally the dopant concentration near the substrate
4
surface is low. At the same time, the vertically retrograde profile
5
a
provides the highest p-type dopant concentration 6 areas below the surface which advantageously tend to block subsurface currents and further redirect the source/drain current toward the surface.
Profile
5
b
is laterally graded toward the center of the channel (and across the channel) from the regions of the highest p-type concentration 6 for maintaining and controlling the Vt roll-off. Profile
5
c
is diagonally graded toward the source/drain regions to minimize tunneling current and body-to-source/drain junction capacitance (Cjbw).
Further, the retrograde profile associated with the lower channel portion would ideally extend under the source/drain regions to minimize the body-to-source/drain junction capacitance (Cjbw), to minimize tunneling current, and to minimize the source-drain resistance Rsd. The Rsd would be minimized because less compensation of the dose to the highly doped source/drain areas would be required. A low Rsd allows less potential (voltage) drop across the highly doped source/drain region, thus more potential will drop across the channel
2
a
. It is the amount of potential drop across the channel that determines the amount of drive current.
Together, profiles graded in the above manner would provide halos centered around the high p-type concentration 6 areas, and would tend to direct source/drain current toward the substrate surface while blocking subsurface currents, control Vt roll-off, and minimize Cjbw, tunneling current and Rsd.
In addition, as device densities and operational speeds continue to increase, reduction of the delay times in the MOS devices used in integrated circuits is desired. These delays are related to the on-state resistance as well as the junction capacitances of these MOS devices. In order to reduce these delays and increase MOS device speeds, improved halo profiles as indicated are desired. Further, increasing device densities also result in a reduced source to drain distance, which requires that halo dopant concentrations increase and move closer to the surface of the substrate. These changes may result in a disruption to the operation of a MOS transistor. In these and similar circumstances, a vertically retrograde profile may help to avoid or mitigate some of the problems encountered in the scaling of MOS devices.
Several prior art methods have been used to create halo-type structures. One such method is the “solid source diffusion” approach, which creates a halo-type structure from a highly doped spacer.
FIGS. 2A-2D
illustrate a prior art method of forming a halo-type structure in a MOS transistor
20
according to the “solid source diffusion” method. Initially in
FIG. 2A
, the MOS transistor
20
comprises a gate structure
21
formed over a semiconductor substrate
22
. Gate structure
21
comprises a gate-oxide material layer
24
formed over the semiconductor substrate
22
, a polysilicon material layer
26
formed over the g

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