Method to prevent CMP overpolish

Details Method to prevent CMP overpolish Method to prevent CMP overpolish

1998-10-05

2001-03-20

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Combined with the removal of material by nonchemical means

C438S692000, C438S633000, C438S760000, C438S244000, C438S253000

Reexamination Certificate

active

06204195

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of chem.-mech. polishing with particular reference to dishing effects.
BACKGROUND OF THE INVENTION
As the dimensions of integrated circuits continue to shrink, problems that had previously not shown themselves begin to emerge. An example of this occurs when CMP (chemical mechanical polishing) is used as the final step of a planarization process during the manufacture of an integrated circuit. In
FIG. 1
we show a schematic representation of the problem. After via hole
13
was formed in dielectric layer
10
, it was filled with a plug of a suitable conductive material, following which a metallic layer was deposited onto the surface of
10
and then patterned into the shape of the line
12
(whose direction is into the plane of the drawing). This structure was then covered with a planarizing layer
11
. Initially, layer
11
is made thick enough so that all steps on the surface are fully covered. Layer
11
is then heated to the point that it softens thereby planarizing the surface. At this stage layer
11
is too thick so it needs to be reduced to a thickness such that layer
12
is either exposed or, more commonly, only just covered.
The etching technique used to reduce the thickness of
11
is often CMP because of its tendency to provide a planar etch front rather than to follow the initial contours of the surface. Particularly if layer
11
comprises a relatively soft material (such as, for example, boro-phosphosilicate glass) there is a tendency for ‘dishing’ to occur in the vicinity of the step formed by line
12
, as illustrated in the figure.
In the course of searching for prior art that provided a way to deal with this problem we were unable to find the solution taught by the present invention. However, a number of references of interest were found. For example, Auer et al. (U.S. Pat. No. 5,714,779 February 1998) show a capacitor having two dielectric layers that are processed by CMP leaving only one behind on the capacitor. There is however no indication that the layer that is left behind is acting as a CMP stop layer or that it needs to be hard.
Lin (U.S. Pat. No. 5,663,108 September 1997) shows a capacitor that has an oxide layer over a SOG layer and then uses CMP to planarize the SOG layer. Linliu et al. {U.S. Pat. No. 5,688,713 November 1997) shows a cylindrical capacitor while Lee (U.S. Pat. No. 5,748,521 May 1998) shows a capacitor covered by a planarized dielectric layer.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a method for planarizing a layer on the surface of an integrated circuit.
Another object of the invention has been to use CMP to accomplish the planarizing but without introducing any dishing.
A further object of the invention has been that said method be easy to apply and be fully compatible with standard IC manufacturing techniques.
These objects have been achieved by first coating the surface to be planarized with a layer of a hard dielectric material, such as silicon nitride, prior to depositing the planarizing medium. After the latter has been reflowed, its thickness is reduced by means of CMP. While CMP is being applied, the etch rate is constantly sensed. When the etch front approaches the aforementioned hard layer a decrease in the etch rate is sensed and etching is terminated, thereby eliminating any dishing effects.


REFERENCES:
patent: 5663108 (1997-09-01), Lin
patent: 5688713 (1997-11-01), Linliu et al.
patent: 5714779 (1998-02-01), Aver et al.
patent: 5748521 (1998-05-01), Lee
patent: 5879981 (1999-03-01), Tanigawa
patent: 6008085 (1999-12-01), Sung et al.
patent: 6022807 (2000-02-01), Lindsey, Jr. et al.

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