Method to preserve the testing chip for package's quality

Details Method to preserve the testing chip for package's quality Method to preserve the testing chip for package's quality

1999-06-01

2001-08-14

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C324S765010, C324S762010, C438S017000

Reexamination Certificate

active

06274397

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the field of semiconductor circuit manufacturing, and more specifically to the field of preventing exposed metal line corrosion prior to the testing of semiconductor devices.
(2) Description of the Prior Art
Multi chip modules and other electronic devices are constructed using unpackaged or bare semiconductor dice. These unpackaged dice are, during the semiconductor manufacturing process, tested and burned in to assure that each die is a known good die. This has led to the creation of test carriers where a single or a multiplicity of die are assembled and tested and whereby the test carrier provides for electrical interaction between the die pads and external test circuitry.
It has been suggested that, during testing, a circuit forms on the die that causes pad leakage. This pad leakage can occur from the input or output pads on a die to other pads on the die such as ground pads, power pads and bias voltage pads. Pad leakage can further occur from a pad to the silicon substrate of a die or to another component of the die.
A number of semiconductor package designs include the design of an special circuit that serves to provide an electrical path form the input/output pads to a ground pad, or to a power pad or a bias voltage pad for the die. This electrical path is designed to be actuated by a high voltage, such as an electrostatic discharge, being applied to the input or output pads of the die. These special circuits may become defective further causing a pattern of leakage current across the semiconductor package.
A number of different types of semiconductor circuits can be used to form a VLSI integrated circuit package, circuits such as Pin Grid Array (PGA) and Ball Grid Array (BGA) can be part of this package. These various types of circuit packages can be mounted on a chip carrier where they can be further interconnected by means of conducting lines.
Packaged semiconductor dice are routinely checked for pad leakage and other electrical performance characteristics. A passivation layer is applied across the package over which a molding compound is deposited. The passivation layer is deposited first so that the molding compound can be applied, the passivation layer protects the electronic circuitry from the molding compound. The passivation layer would be deposited only over the electronic circuitry thus leaving the interconnecting conducting lines open and exposed to the atmosphere. These metal lines would therefore be subject to line corrosion. The present invention addresses a method to prevent line corrosion from happening while still being able to cover the completed electronic package with the molding compound.
FIG. 1
shows a Prior Art cross section of the semiconductor circuit package. Active semiconductor circuit chips
10
are shown. Over these chips a layer
12
of Plasma Enhanced oxide is deposited. Further package constructs
14
(dielectric) are indicated. A passivation layer
16
is deposited over constructs
14
and the layer
12
of PE oxide where this layer is in the immediate physical proximity of the active circuits
10
. This passivation layer
16
shields the semiconductor circuits from the environment and from the to be deposited molding compound
20
. The passivation layer further provides improved adhesion of the molding compound to the substrate, it reduces stress between the surface of the die and the molding compound, it improves resistance to moisture susceptibility and it decreases exposure to soft-error failure.
Area
19
as shown in
FIG. 1
is a sub-section of the deposited molding compound
20
, the passivation layer
16
has been deposited in this area. Area
21
is also a sub-section of the deposited molding compound
20
, this area has been designed for corrosion testing and the passivation layer (
16
, for area
19
) is therefore not deposited in this area. Area
19
contains the thermal stress test pattern, this thermal stress is measured by measuring the leakage current between the pattern
10
and the pattern
18
.
Also shown are metal lines
18
, these metal lines are, in the interval between formation of the semiconductor package (marked by the deposition of the passivation layer
16
) and the formation of the molding compound
20
, exposed to the atmosphere. This interval can last over a considerable length of time, up to weeks or even months. This exposure subjects the metal lines to atmospheric corrosive action that results in corrosion of the metal lines.
U.S. Pat. No. 5,366,589 (Chang) shows a passivation film over a bonding pad to prevent corrosion.
U.S. Pat. No. 5,490,324 (Newman) shows pads with molding compounds thereover.
U.S. Pat. No. 5,731,246 (Bakeman) shows a process to protect aluminum metallization against chemical attack during photoresist development.
SUMMARY OF THE INVENTION
It is the primary objective of the invention is to prevent corrosion of exposed conducting lines within a semiconductor package.
In accordance with the primary objective of the invention a method is presented for the elimination of metal line corrosion for semiconductor packages where metal lines are exposed to the atmosphere for an extended period of time. A passivation layer is deposited over the active die of the semiconductor package, a layer of polymer film is deposited over the passivation layer and over the exposed conducting lines. At the time that the semiconductor package must be tested, including testing for corrosion of the exposed metal lines, the polymer layer is removed, the molding compound is formed and the package is tested. The added step of depositing a layer of polymer film has protected the interconnecting conducting lines from corrosion.


REFERENCES:
patent: 4173820 (1979-11-01), Mueller et al.
patent: 5366589 (1994-11-01), Chang
patent: 5490324 (1996-02-01), Newman
patent: 5731246 (1998-03-01), Bakeman, Jr. et al.
patent: 5793118 (1998-08-01), Nakajima
patent: 5837558 (1998-11-01), Zuniga et al.
patent: 5858806 (1999-01-01), Nishida
patent: 5925260 (1999-07-01), Jiang
patent: 6114181 (2000-09-01), Gregoritsch, Jr.

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