Method to pattern small features by using a re-flowable hard...

Details Method to pattern small features by using a re-flowable hard... Method to pattern small features by using a re-flowable hard...

2002-02-08

2004-12-07

Duda, Kathleen (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S330000, C216S051000

Reexamination Certificate

active

06828082

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of patterning small features used in the fabrication of semiconductor devices.
BACKGROUND OF THE INVENTION
Current practices for patterning small features typically involve using smaller wavelengths of light to pattern photoresist, or using an ashing process to reduce the dimensions of photoresist after some larger-dimension features are patterned.
U.S. Pat. No. 4,022,932 to Feng describes a resist reflow method for making submicron patterned resist masks.
U.S. Pat. No. 5,899,746 to Mukai describes a method for making small patterns by eroding a photoresist pattern.
U.S. Pat. No. 4,824,747 to Andrews describes a method for forming a variable width channel.
U.S. Pat. No. 4,449,287 to Maas et al. describes a method of providing a narrow groove or slot in a substrate region.
U.S. Pat. No. 4,546,066 to Field et al. describes a method for forming narrow images on semiconductor substrates.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved method of patterning small features.
Another object of the present invention to provide an improved method of patterning small features that does not place more stringent requirements upon lithography.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer. A small feature material is formed within the second opening. Any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.


REFERENCES:
patent: 4022932 (1977-05-01), Feng
patent: 4256514 (1981-03-01), Pogge
patent: 4449287 (1984-05-01), Maas et al.
patent: 4546066 (1985-10-01), Field et al.
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4824747 (1989-04-01), Andrews
patent: 5899746 (1999-05-01), Mukai

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