Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-01-30
2004-03-09
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S719000, C438S723000, C438S906000
Reexamination Certificate
active
06703317
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor wafer manufacturing and more particularly to a method for reducing electrical charge imbalances produced by an electrical charge producing wafer cleaning process.
BACKGROUND OF THE INVENTION
In creating a multiple layer semiconductor device on a semiconductor wafer, each layer making up the device may be subjected to one or more deposition processes, for example using chemical vapor deposition (CVD) or physical vapor deposition (PVD) , and usually including one or more etching procedures by either a dry (plasma) or wet (chemical) etching process. A critical condition in semiconductor manufacturing is the absence of contaminants on the wafer processing surface, since contaminants including, for example, microscopic particles, may interfere with and adversely affect subsequent processing steps leading to device degradation and ultimately semiconductor wafer rejection.
While the wafer cleaning process has been always been a critical step in the semiconductor wafer manufacturing process, ultraclean wafers are becoming even more critical to device integrity. For example, as semiconductor feature sizes decrease, the detrimental affect of particle contamination increases, requiring removal of ever smaller particles. For example, particles as small as 5 nm may be unacceptable in many semiconductor manufacturing processes. Further, as the number of device layers increase, for example to 5 to 8 layers, there is a corresponding increase in the number of cleaning steps and the potential for device degradation caused by particulate contamination. To adequately meet requirements for ultraclean wafers in ULSI and VLSI the wafer surface must be essentially free of contaminating particles.
For example, insulating dielectric layers also referred to as inter-metal dielectric (IMD) layers are typically deposited by plasma enhanced CVD (PECVD) or high density plasma CVD (HDP-CVD). In these deposition processes a degree of sputtering occurs as the layer of material is deposited causing a higher degree of particulate contamination as the deposition time increases. In addition, PVD processes are typically used to deposit films of metal, for example barrier/adhesion layers within anisotropically etched features or for metal filling an anisotropically etched feature. PVD processes tend to coat the inner surfaces of the processing chamber with a metal film, flaking off to contaminate a wafer process surface as the metal film increases in thickness and are subjected to cyclic thermal stresses. The degree of particulate contamination depositing on the process surface increases with the thickness of the film being deposited.
To overcome the problem of particulate contamination which can lead to “killer defects” wafer process surface cleaning processes increasingly use a combination of spraying with a high pressure cleaning solution and scrubbing the wafer surface with a rotating brush including specialized bristles to avoid scratching the wafer process surface.
One increasingly critical problem with several semiconductor wafer manufacturing processes is the tendency of the process to produce electrical charge imbalances at the wafer surface. The presence of electrical charge imbalances may lead to a variety of problems in subsequent processes. Increasingly important in wafer process technologies as device sizes shrink is the effect of electrical charge imbalance produced at the wafer surface which has not been adequately addressed by prior art processes. Electrical charge imbalances at the wafer surface may lead to subsequent processing difficulties, for example in plasma enhanced deposition processes where the presence of electrical charge imbalances may affect the plasma process leading to a reduced wafer yield.
There is therefore a need in the semiconductor processing art to develop a method whereby an electrical charge imbalance at a semiconductor wafer process surface is avoided following a particulate cleaning process to improve a subsequent processing step including a wafer manufacturing yield.
It is therefore an object of the invention to provide a method whereby an electrical charge imbalance at a semiconductor wafer process surface is avoided following a particulate cleaning process to improve a subsequent processing step including a wafer manufacturing yield, while overcoming other shortcomings and deficiencies of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method of reducing an electrical charge imbalance on a wafer process surface.
In a first embodiment, the method includes providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.
REFERENCES:
patent: 5039349 (1991-08-01), Schoeppel
patent: 5421902 (1995-06-01), Odajima et al.
patent: 5723383 (1998-03-01), Kosugi et al.
patent: 5795401 (1998-08-01), Itoh et al.
patent: 5811358 (1998-09-01), Tseng et al.
patent: 5834371 (1998-11-01), Ameen et al.
patent: 5968279 (1999-10-01), MacLeish et al.
patent: 5996594 (1999-12-01), Roy et al.
patent: 6007675 (1999-12-01), Toshima
patent: 6058945 (2000-05-01), Fujiyama et al.
patent: 6079426 (2000-06-01), Subrahmanyam et al.
patent: 6090217 (2000-07-01), Kittle
patent: 6204192 (2001-03-01), Zhao et al.
patent: 6221774 (2001-04-01), Malik
patent: 6358325 (2002-03-01), Andreas
patent: 6432479 (2002-08-01), Chang et al.
patent: 6613242 (2003-09-01), Nakahara et al.
Cheng Yi-Lung
Wang Ying-Lung
Wu Sze-An
Yoo Ming-Hwa
Lebentritt Michael S.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
LandOfFree
Method to neutralize charge imbalance following a wafer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to neutralize charge imbalance following a wafer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to neutralize charge imbalance following a wafer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3226055