Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-03-16
2003-03-04
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S241000, C438S655000
Reexamination Certificate
active
06528422
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor memory devices and more specifically to methods to improve
1
T-RAM 0.25 &mgr;m logic-based DRAM.
BACKGROUND OF THE INVENTION
1
T-RAM is a logic-based DRAM that easily fails due to high junction leakage current created by the logic process. In the current process, resist protect oxide (RPO) is used where it is desired that silicidation not take place, for example ESD device or non-silicide resistor.
U.S. Pat. No. 6,015,730 to Wang et al. and U.S. Pat. No. 5,863,820 to Huang each describe salicide processes with a resist protect oxide (RPO) protective step.
U.S. Pat. No. 6,048,738 to Hsu et al. describes a process for fabricating a
1
T ferroelectric random access memory (FRAM) for a VLSI RAM array.
U.S. Pat. No. 6,091,106 to Park describes an SRAM process forming a transistor structure having a grooved gate.
U.S. Pat. No. 5,918,148 to Sato describes a
1
T SRAM process wherein the reduction in product quality and yield due to the partial reduction in restoring level, a lag of timing, can be avoided.
U.S. Pat. No. 5,434,438 to Kuo describes a
1
T and one capacitor memory device.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an RPO method to reduce junction leakage of
1
T-RAM logic base DRAM.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.
REFERENCES:
patent: 5434438 (1995-07-01), Kuo
patent: 5863820 (1999-01-01), Huang
patent: 5918148 (1999-06-01), Sato
patent: 5998252 (1999-12-01), Huang
patent: 6004843 (1999-12-01), Huang
patent: 6015730 (2000-01-01), Wang et al.
patent: 6048738 (2000-04-01), Hsu et al.
patent: 6074915 (2000-06-01), Chen et al.
patent: 6091106 (2000-07-01), Park
patent: 6093593 (2000-07-01), Jang
patent: 6187655 (2001-02-01), Wang et al.
patent: 6194258 (2001-02-01), Wuu
patent: 6319784 (2001-11-01), Yu et al.
patent: 6350636 (2002-02-01), Lee et al.
Chen Chih-Chang
Chin Pin-Shyne
Huang Ching-Kwun
Peng Hsien-Chih
Ackerman Stephen B.
Chaudhuri Olik
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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