Method to manufacture silicon quantum islands and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S009000, C257SE21090, C257SE29170, C257SE21404, C438S962000

Reexamination Certificate

active

07939398

ABSTRACT:
A method of manufacturing a single-electron transistor device is provided. The method includes forming a thinned region in a silicon substrate, the thinned region offset by a non-selected region. The method also includes forming at least one quantum island from the thinned region by subjecting the thinned region to an annealing process. The non-selected region is aligned with the quantum island and tunnel junctions are formed between the quantum island and the non-selected region. The present invention also includes a single-electron device, and a method of manufacturing an integrated circuit that includes a single-electron device.

REFERENCES:
patent: 4788160 (1988-11-01), Havemann et al.
patent: 5327375 (1994-07-01), Harari
patent: 5608231 (1997-03-01), Ugajin et al.
patent: 5731598 (1998-03-01), Kado et al.
patent: 6060743 (2000-05-01), Sugiyama et al.
patent: 6066872 (2000-05-01), Okada et al.
patent: 6093243 (2000-07-01), Okada et al.
patent: 6211531 (2001-04-01), Nakazato et al.
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6414333 (2002-07-01), Lee et al.
patent: 6444545 (2002-09-01), Sadd et al.
patent: 6487112 (2002-11-01), Wasshuber
patent: 6524883 (2003-02-01), Kim
patent: 6756292 (2004-06-01), Lee et al.
patent: 0642173 (1995-03-01), None
patent: WO9415340 (1994-07-01), None
patent: WO9853504 (1998-11-01), None
“TSR Quantum Dots and Their Application to Nanometer-Size Memory Devices,” Fujitsu Sci. Tech. J., 34, Dec. 1998, pp. 162-181 (Yoshiki Sakuma, Yuji Awano and Masashi Shima).
Self-Assembled Ge Dots: Growth Characterization, Ordering, and Applications, J. Vac. Sci. Technol., B, 16 (1998), pp. 1575-1581 (P. Schittenhelm, et al).
“Thermal Agglomeration of Single-Crystalline Si Layer on Buried SiO2 in Ultrahigh Vacuum,” J. Vac. Sci. Technol. B, 20(1), Jan./Feb. 2002, pp. 167-172 (Ratno Nuryadi, Yasuhiko Ishikawa, Yukinori Ono and Michiharu Tabe).
“Single-Electron Tunneling Effects in Granular Metal Films,” American Physical Society, vol. 50, No. 12, Sep. 15, 1994, pp. 8961-8965 (E. Bar-Sadeh, Y. Goldstein, C. Zhang, H. Deng, B. Abeles, and O. Millo).
“Formation of Gold Particles at a Functional LB Film/Gold Interface Leading to Coulomb Blockade Phenomena,” Synthetic Metals 94 (1998), pp. 141-144 (M. Burghard, G. Philipp, C. Mueller-Schwanneke & S. Roth).
“Coulomb Blockade in Sb Nanocrystals Formed in Thin, Thermally Grown SiO2 Layers by Low-Energy Ion Implantation,” Applied Physics Letters, vol. 73, No. 8, Aug. 24, 1998, pp. 1071-1073 (Anri Nakajima, Hiroshi Nakao, Hiroaki Ueno, Toshiro Futatsugi & Naoki Yokoyama.
“Characteristic Tunnel-Type Conductivity and Magnetoresistance in a CoO-Coated Monodispersive Co Cluster Assembly,” Applied Physics Letters, vol. 74, No. 1, Jan. 4, 1999, pp. 76-76 (D.L. Peng, K. Sumiyama, S. Yamamuro, T. Hihara, and T.J. Konno).
PCT Application No. PCT/AT98/00105, filed Apr. 22, 2009.
“Coulomb Blockade Devices Fabricated by Liquid Metal Ion Source Droplet Deposition,” J. Vac. Sci. Technol. B 16(6), Nov./Dec. 1998, pp. 3789-3794 (C. Vieu, A. Pepin, J. Gierak, C. David, Y. Jin, F. Carcenac, and H. Launois).
“pH-Gated Single-Electron Tunneling in Chemically Modified Gold Nanoclusters,” J. Am Chem. Soc. 1998, pp. 7645-7646 (Louis C. Brousseau, III, Qi Zhao, David A. Shultz, and Daniel L. Feldheim).
“Fabrication and Physics of 2nm Islands for Single Electron Devices,” J.Vac. Sci. Technol. B 13(6), Nov./Dec. 1995, pp. 2883-2887 (Wei Chen, and Haroon Ahmed).
“Room-Temperature Coulomb-Blockade-Dominated Transport in Gold Nanocluster Structures,” Semicond. Sci. Technol. 13 (1998), pp. A11-A114 (L. Clarke, M.N. Wybourne, L. O. Brown, J.E. Hutchison, M. Yan, S.X. Cai and J.F.W. Keana).
“Coulomb Blockade Effect Through a 2D Ordered Array of Pd Islands Obtained by Colloidal Deposition,” Microelectronic Engineering, 1998, pp. 507-510 (c. Lebreton, C. Vieu, A. Pepin, M. Mejias, F. Carcenac, Y. Jin and H. Launois).
“Construction of Semiconductor Nanoparticle Layers on Gold by Self-Assembly Technique,” JPN. J. Appl. Phys., 36 (1997), pp. 4053-4056 (T. Nakanishi, B. Ohtani, K. Uosaki).
“Fabrication and Electrical Characteristics of Single Electron Tunneling Devices Based on Si Quantum Dots Prepared by Plasma Processing,” JPN. J. Appl. Phys, 36, (1997), pp. 4038-4041 A. Dutta, M. Kimura, Y. Honda, M. Otobe, A. Itoh, S. Oda).
“Effect of Patterning on Thermal Agglomeration of Ultrathin Silicon-On-Insulator Layer,” Applied Surface Science 190 (2002), pp. 11-15 (Yasuhiko Ishikawa, Minoru Kumezawa, Ratno Nuryadi and Michiharu Tabe).
“Pattern-Induced Alignment of Silicon Islands on Buried Oxide Layer of Silicon-on-Insulator Structure, ”Applied Physics Letters, vol. 83, No. 15, (Oct. 13, 2003), pp. 3162-3164 (Yasuhiko Ishikawa, Yasuhiro Imai, Hiroya Ikeda and Michiharu Tabe).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method to manufacture silicon quantum islands and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to manufacture silicon quantum islands and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to manufacture silicon quantum islands and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2685693

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.