Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-02-27
2000-07-04
Fahmy, Wael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438443, 257315, 257330, H01L 21336
Patent
active
060837934
ABSTRACT:
A method to fabricate nonvolatile memories with a trench-pillar cell structure is disclosed. A pad oxide is formed on a substrate. A pad nitride is then formed on the pad oxide. An ion implantation is performed to form a lightly doping drain (LDD) in the substrate. The pad nitride, the pad oxide and the substrate are etched to form a trench. A nitride layer is then formed on the pad nitride to fill into the trench. The nitride layer is etched back to form spacers on the sidewalls of the trench. The substrate is etched back to form a subtrench in the trench. Afterward, a polysilicon layer is deposited to refill the trench region and covers a surface of the nitride. The polysilicon is etched back to remove the polysilicon layer on a surface of the nitride. The pad nitride, the nitride and the pad oxide are removed. A tunnel oxide is formed on the pillar, the trench region and the substrate. A floating gate is then formed. The floating is in the trench region and is extended to the top of the trench. An inter-poly oxide is formed on the floating gate. A control gate is formed on the inter-poly oxide. Spacers of the floating gate, the inter-poly oxide and the control gate are formed. Source/drain regions are formed in the substrate. A thick oxide is deposited on the surface of the substrate. A metal contact is formed on the source/drain region.
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Coleman William David
Fahmy Wael
Texas Instruments - Acer Incorporated
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