Method to manufacture multiple damascene by utilizing etch selec

Details Method to manufacture multiple damascene by utilizing etch selec Method to manufacture multiple damascene by utilizing etch selec

1998-10-02

2000-08-22

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

H01L 21311

Patent

active

061072044

ABSTRACT:
A method of manufacturing a semiconductor device having multiple layers of interconnects that are filled in a single conductive material filling step. Two layers of interlayer dielectric separated by an etch stop layer are formed over a layer including metal structures in contact with electrodes of active devices formed in and on a semiconductor substrate. A layer of photoresist is formed on a second etch stop layer formed on the upper layer of interlayer dielectric. The layer of photoresist is patterned and etched. Masking and etching processes form openings in the first and second layers of interlayer dielectric including openings to the metal structures. The openings are filled in a single conductive material filling step.

REFERENCES:
patent: 5741626 (1998-04-01), Jain et al.
patent: 5880018 (1999-03-01), Boeck et al.
patent: 5920790 (1999-07-01), Wetzel et al.
patent: 5960317 (1999-09-01), Jeong

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