Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-09-05
2006-09-05
Lee, Hsien-Ming (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S283000, C438S301000, C438S303000, C438S652000
Reexamination Certificate
active
07101746
ABSTRACT:
A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.
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Co-pending U.S. Appl. No. 10/697,746, filed on Oct. 30, 2003 to T. H. Chan.
Co-pending U.S. Appl. No. 10/266,425, filed on Oct. 8, 2002 to Chew-Hoe Ang et al.
Bhat Mousumi
Chan Tze Ho Simon
Chee Jeffrey
Ackerman Stephen B.
Chartered Semiconductor Manufacturing Ltd.
Lee Hsien-Ming
Saile Ackerman LLC
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