Method to increase the surface area of a storage node electrode,

Details Method to increase the surface area of a storage node electrode, Method to increase the surface area of a storage node electrode,

1996-11-06

1998-08-11

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438397, 438240, H01L 218242

Patent

active

057926883

ABSTRACT:
A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a lower, or storage node electrode, for the STC structure, consisting of a flat, polysilicon plug, contacting an underlying transistor region, and of an upper polysilicon shape, comprised of polysilicon columns, extending between about 2500 to 6000 Angstroms, above the top surface of the flat, polysilicon plug. The flat, polysilicon plug is formed via creation of a capacitor contact hole, in an insulator layer, followed by polysilicon deposition, and RIE etch back, creating the flat, polysilicon plug, recessed in a lower portion of the capacitor contact hole. Another polysilicon deposition, and anisotropic RIE procedure, results in the formation of polysilicon columns, on the sides of the upper portion of the capacitor contact hole. Removal of insulator layers expose the storage node electrode, comprised of polysilicon columns, overlying, and extending above, the underlying flat, polysilicon plug.

REFERENCES:
patent: 5084405 (1992-01-01), Fazan et al.
patent: 5290729 (1994-03-01), Hayashide et al.
patent: 5447882 (1995-09-01), Kim
patent: 5580811 (1996-12-01), Kim

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