Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-04-05
2011-04-05
Pham, Thanhha (Department: 2894)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S593000, C438S734000, C257SE21179
Reexamination Certificate
active
07919367
ABSTRACT:
A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.
REFERENCES:
patent: 4811076 (1989-03-01), Tigelaar et al.
patent: 5108941 (1992-04-01), Paterson et al.
patent: 5198995 (1993-03-01), Dennard et al.
patent: 5301150 (1994-04-01), Sullivan et al.
patent: 5365486 (1994-11-01), Schreck
patent: 5394365 (1995-02-01), Tsukikawa
patent: 5414671 (1995-05-01), Fukumoto
patent: 5479367 (1995-12-01), Maurelli et al.
patent: 5504706 (1996-04-01), D'Arrigo et al.
patent: 5511020 (1996-04-01), Hu et al.
patent: 5554552 (1996-09-01), Chi
patent: 5600598 (1997-02-01), Skjaveland et al.
patent: 5654237 (1997-08-01), Suguro et al.
patent: 5694355 (1997-12-01), Skjaveland et al.
patent: 5696036 (1997-12-01), Su et al.
patent: 5699297 (1997-12-01), Yamazaki et al.
patent: 5700708 (1997-12-01), Chen et al.
patent: 5723355 (1998-03-01), Chang et al.
patent: 5736764 (1998-04-01), Chang
patent: 5736765 (1998-04-01), Oh et al.
patent: 5761126 (1998-06-01), Chi et al.
patent: 5783470 (1998-07-01), Rostoker
patent: 5879990 (1999-03-01), Dormans et al.
patent: 5940324 (1999-08-01), Chi et al.
patent: 5953255 (1999-09-01), Lee
patent: 6017792 (2000-01-01), Sharma et al.
patent: 6060403 (2000-05-01), Yasuda et al.
patent: 6064107 (2000-05-01), Yeh et al.
patent: 6064595 (2000-05-01), Logie et al.
patent: 6102963 (2000-08-01), Agrawal
patent: 6145069 (2000-11-01), Dye
patent: 6180453 (2001-01-01), Sung et al.
patent: 6218234 (2001-04-01), Yu et al.
patent: 6221007 (2001-04-01), Green
patent: 6232631 (2001-05-01), Schmidt et al.
patent: 6256248 (2001-07-01), Leung
patent: 6278159 (2001-08-01), Patelmo et al.
patent: 6282123 (2001-08-01), Mehta
patent: 6329240 (2001-12-01), Hsu et al.
patent: 6415353 (2002-07-01), Leung
patent: 6449685 (2002-09-01), Leung
patent: 6504780 (2003-01-01), Leung
patent: 6512691 (2003-01-01), Hsu et al.
patent: 6548355 (2003-04-01), Pio
patent: 6590570 (2003-07-01), Maki
patent: 6803299 (2004-10-01), Eitan
patent: 6898140 (2005-05-01), Leung et al.
patent: 6977408 (2005-12-01), Lin et al.
patent: 7200038 (2007-04-01), Lee et al.
patent: 7257033 (2007-08-01), Wang et al.
patent: 7447064 (2008-11-01), Bu et al.
patent: 2002/0015327 (2002-02-01), McPartland et al.
patent: 2003/0032241 (2003-02-01), Seo et al.
patent: 2004/0021166 (2004-02-01), Hyde et al.
patent: 2005/0074935 (2005-04-01), Hsu
patent: 2005/0173753 (2005-08-01), Kim et al.
patent: 2005/0281087 (2005-12-01), Shirota et al.
patent: 2006/0186947 (2006-08-01), Lin et al.
Shukuri et al. “CMOS Process Compatible ie-Flash(inverse gate electrode Flash) Technology for System-on-a-Chip”, IEEE 2001 Custom Integrated Circuits Conference, pp. 179-182.
Takeshima et al. “A 3.3 V Single-Power-Supply 64Mb Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme”, 1994 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 148-149.
Houdt et al. “Analysis of the Enhanced Hot-Electron Injection in Split-Gate Transistors Useful for EEPROM Applications”, IEEE Transactions on Electron Devices, vol. 39, No. 5, May 1992, pp. 1150-1156.
Fang Gang-Feng
Leung Wingyu
Sinitsky Dennis
Bever Hoffman & Harms LLP
Hoffman E. Eric
MoSys, Inc.
Pham Thanhha
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