Method to improve yield for capacitors formed using etchback of

Details Method to improve yield for capacitors formed using etchback of Method to improve yield for capacitors formed using etchback of

1997-06-23

1999-02-23

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438398, H01L 218242

Patent

active

058743367

ABSTRACT:
A method is described for forming capacitor plates with extended surface area using polysilicon hemispherical grains or HSG polysilicon. The HSG polysilicon is formed on the top surface and sidewalls of first capacitor plates. A vertical anisotropic etching step forms an irregular top surface of the first capacitor plates and an anneal step provides good adhesion between the grains of HSG polysilicon and the sidewalls of the first capacitor plates. A timed etchback of the dielectric between the first capacitor plates insures good electrical insulation between adjacent first capacitor plates.

REFERENCES:
patent: 5082797 (1992-01-01), Chan et al.
patent: 5134086 (1992-07-01), Ahn
patent: 5254503 (1993-10-01), Kenney
patent: 5256587 (1993-10-01), Jun et al.
patent: 5358888 (1994-10-01), Ahn et al.
patent: 5447878 (1995-09-01), Park et al.
patent: 5492848 (1996-02-01), Lur et al.
patent: 5622889 (1997-04-01), Yoo et al.
"A Capacitor-Over-Bit-Lhe (COB) Cell with a Hemispherical Grain Storage Node for 64 MbDRAMS" by Sakao et al, IEDM, 1990, pp. 27.31-27.34.

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